modelsim: Types do not match

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Hi,

I'm a beginner in VHDL.
I'm trying to implement the xess-sdram controller. When I try to
simulate it, I keep getting errors from modelsim like: 'Types do not
match..'. But they are the same type.
I stripped it now down to nothing else than the controller and some
signals in the file. But still the errors occure. Any hints?

for example:
----8<----
...
component sdramCntl is
     generic (
         ...
         );
     port (
         ...
         sDIn:  in  unsigned(DATA_WIDTH-1 downto 0);  -- data from SDRAM
         sDOut: out unsigned(DATA_WIDTH-1 downto 0);  -- data to SDRAM
         );
...
signal sdram_data_in    : unsigned(SD_DATA_BUS_WIDTH-1 downto 0);
signal sdram_data_out   : unsigned(SD_DATA_BUS_WIDTH-1 downto 0);
...
port map (
     ...
     sDin        => sdram_data_in,
     sDOut       => sdram_data_out,
     ...
     );
---->8----

Error message from modelsim:
----8<----
...
# WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port sdin
# WARNING[1]: memory_tester_2_top.vhd(183): A use of this default
binding for this component instantiation will result in an elaboration
error.
# WARNING[1]: memory_tester_2_top.vhd(183): Types do not match for port
sdout
# WARNING[1]: memory_tester_2_top.vhd(183): A use of this default
binding for this component instantiation will result in an elaboration
error.
...
---->8----

Thanks
   André Schieleit

Re: modelsim: Types do not match
André,

What are the values of DATA_WIDTH and SD_DATA_BUS_WIDTH ?
What is the generic part of your component for ?

Nicolas Pinault


André Schieleit a écrit :
Quoted text here. Click to load it

Re: modelsim: Types do not match
Quoted text here. Click to load it

You have clipped too much for an answer. But it appears the messages
mean that your declaration of the component sdramCntl where it is coded
does not match the declaration where it is used. The messages have
nothing to do with sdram_data_in/out.

Re: modelsim: Types do not match
thanks for your answers.
after some research I eventually found out, that using both
IEEE.STD_LOGIC_ARITH.ALL and IEEE.numeric_std.all was causing my problem.

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