Hello Group,
Thank you all for the help with my last question.
I have another issue with the Behaviour vs. PAR models as it relates to FIFOs. I find that in the behavior model the read cycle looks as if it takes two clock cycles to get new data and in the PAR model the data comes more readily, around 11ns, about half a cycle.
I suspect that the Behavior model might be two cycles delay since the Read_Enable sets up on a rising edge of a clock. However the read cycle does not initiate until one cycle later, when the Read_Enable is high, albeit going low. And then there is one more clock delay in the read output.
If I were modeling this on the top level I would delay my clock a tad, so the read enable was already set up, and then the output would come one cycle later, not two. Unfortunetely, this is an instantiated component in a lower level, wherein the read enable is generated by the same clock that runs the FIFO. I guess this is the problem of infinitely fine timing units called deltas?
It would be an ugly and time consuming process to run everything through the PAR and post sim. I suppose I could run a separate clock, down the hierarchy to run just the FIFO, for simulation purposes. But I am hoping that this group knows a better solution.
Thanks,
Brad Smallridge b r a d @ a i v i s i o n . c o m