Hello, I'm seeing something very fundamentally wrong with my simulation in my testbench simulation.
All inputs to the DUT look fine, but on the other side of input buffers (IBUF & IBUFG), all signals are 'Z'. I instantiate the i/o buffers as I always have done and never had this issue with other simulators (nc-verilog, vcs). Nothing special about the signals - they are straight inputs.
I assume it's something about Modelsim (I'm rather new to this simulator). What am I forgetting to do?
Thanks.
Can you give some more details, like: what are the models you are using for IBUF and IBUFG, whether it is RTL/Post-synthesis/Post-PAR simulation. And finally whether it is VHDL or Verilog !
Vikram
Oh, sorry.
I'm using verilog and it is an RTL simulation. I had compiled the primitives by : compxlib -s mti_pe -f all -l all -o C:\modeltech_xxx\xilinx_libs.
I'm using unisim - I assume that's what you mean by 'models'?
My search turned up a similar thread, but it didn't offer any solution or replies.
Typically when simulating with Xilinx primitives, I'll just add the primitive library files into my modelsim project as needed. In your case, I would add IBUF.v and IBUFG.v, then compile my whole project and start simulating. I've never had much luck pointing or creating libraries with ModelSim.
Hope this helps,
Jeremy
Yes, compiling the library files along with the project is probably a good way to find out the problem. You can do this by the command
vlog -y C:/Xilinx/verilog/src/unisims +libext+.v your_DUT.v
(if C:/Xilinx is your Xilinx installation directory) and then run the simulation as usual.
Vikram
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