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Hi All,
Thank you all for your kind replies, Brian, sepher, Berry. I did think it looked suspicious that I had no actual filename for the .sdf file in there. Xilinx tech. support said that "It looked like I didn't have a UUT VHDL file," even though I sent him my entire project, making the question of whether I had one or not a matter of fact to one who knows the correct file name, which now looks like it should be "C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\user_logic_timesim.vhd". Looking at my GUI, in the Sources (for: Post-Route Simulation) window, under my tbw file, I had a document icon labeled "UUT" to its right, and in it I had an orange check mark. This indicated to me that I probably didn't have some kind of required UUT VHDL file, so I called up my FAE (Field Applications Engineer), and he realized that in order to have that created, the following library has to be specified in the top level design (VHDL) file, outside of the design (entity and architecture) area.
-- synopsys translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on
This confirmed a fragment that I had found on the web. Searching for "Warning: (vlib-34) Library already exists at "work"" turned up
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, which said
-------------------------- Article: 62152 Subject: Re: please help, modelsim does not simulate From: snipped-for-privacy@ihug.com.au (Garry Allen) Date: 20 Oct 2003 18:31:49 -0700
This happens because Modelsim is not finding the appropriate library declaring bufg...
at the top of your vhdl file when you include the libraries add something like
-- synopsys translate_off library UNISIM; use UNISIM.VCOMPONENTS.ALL; -- synopsys translate_on
-------------------------- I added that, and rebuilt down to and including "Generate Post-Place & Route Simulation Model", and then I had something in there for the UUT: C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\user_logic_timesim.vhd.
Then in "ModelSim Simulator" in the Processes Window, with "Simulate Post-Place & Route Model" under it. I double- clicked on that and got the following transcript after ModelSim comes up, in the ModelSim transcript (output) window:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # do {user_logic_tbw.tdo} # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8
2006 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading package vital_primitives # -- Loading package textio # -- Loading package vpackage [compiling entities and architectures - all (snipped)] # -- Loading package standard # Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8
2006 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity user_logic_tbw # -- Compiling architecture testbench_arch of user_logic_tbw # vsim -lib work -sdfmax /UUT=netgen/par/user_logic_timesim.sdf -t 1ps user_logic_tbw # Loading C:\Modeltech_xe_starter\win32xoem/.
./std.standard # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading work [snipped] # Loading C:\Modeltech_xe_starter\win32xoem/../vital2000.vital_timing(body) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vcomponents # Loading C:\Modeltech_xe_starter\win32xoem/.
./vital2000.vital_primitives(body) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vpackage(body) [Loading work (snipped - 3 lines)] # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_sff(x_sff_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v) # Loading work [snipped] # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ramb16(x_ramb16_v) [Loading work (snipped - 5 lines)] # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv(x_dcm_adv_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv_clock_divide_by_2(x_dcm_adv_clock_divide_by_2_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv_maximum_period_check(x_dcm_adv_maximum_period_check_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_dcm_adv_clock_lost(x_dcm_adv_clock_lost_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_srlc16e(x_srlc16e_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v) [Loading my designed instances (snipped)] # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_and2(x_and2_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_obuf(x_obuf_v) #
** Warning: Design size of 147314 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity. # Expect performance to be quite adversely affected. #
** Note: (vsim-3587) SDF Backannotation Successfully Completed. # Time: 0 ps Iteration: 0 Region: /user_logic_tbw File: user_logic_tbw.vhw # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf # .main_pane.workspace # .main_pane.signals.interior.cs #
** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.187 ns; Observed := 0.132 ns; At : 0.335 ns # Time: 335 ps Iteration: 3 Instance: /user_logic_tbw/uut/inst_dcm_cg/dcm_autocalibration_dcm_adv_inst/dcm_adv_inst_ro_fd1 #
** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.187 ns; Observed := 0.132 ns; At : 0.335 ns # Time: 335 ps Iteration: 3 Instance: /user_logic_tbw/uut/inst_dcm_cg/dcm_autocalibration_dcm_adv_inst/dcm_adv_inst_ro_fd2 #
** Failure: Simulation successful (not a failure). No problems detected. # Time: 2950 ns Iteration: 0 Process: /user_logic_tbw/line__96 File: user_logic_tbw.vhw # Break at user_logic_tbw.vhw line 280 # Simulation Breakpoint: Break at user_logic_tbw.vhw line 280 # MACRO ./user_logic_tbw.tdo PAUSED at line 14
As you can see the vsim command line now has the correct filename: # vsim -lib work -sdfmax /UUT=netgen/par/user_logic_timesim.sdf -t 1ps user_logic_tbw .
And my post-PAR simulation gave correct results in the final output, since I simulated with a conservatively slow clock of 50ns period (T). Now my only concern is those two simulator warnings.
Cheers,
-James