Hi All, I am trying to sim my design that deals with data transfer between my FPGA and a microcontroller with a 16-bit multiplexed data/address bus. In my design, I am using flags (data_in_enable, data_out_enable) to pick/put data from/onto the bus. Does anyone have an idea how to model the simulation (especially Procssor read cycle) I appreciate all the responses Thanks Morpheus
- posted
19 years ago