Modeling two dimensional circuits

Hello all, I am now trying to code a bough wooley multiplier in verilog. The following link gives good animation and VHDL code for that.

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Is it possible to get a verilog code as simple as the VHDL code shown in the site. i tried to model it but have some doubt.

Is it possible to instantiate two dimensional components in verilog. There is options for 1 dimensional instantiations But when i tried for two dimension it gave an error. I tried the following syntax.. FA fa[7:0][6:0](in1[7:0][6:0],out[7:0][6:0]); etc.... but FA fa[7:0](in1[7:0],out[7:0]); worked just fine. Also i felt like books and related topics on this type advanced design is very less. Requesting evry bodies comment on this. regards Sumesh

Reply to
vssumesh
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I sucess fully created a two dimensional structure for unsigned multiplier, using multiple "one dimensional instantiations". it synthesized correctly but simulator gave error values. All code seems ok i also verified it in the output of the synthesizer but in simulator its not working. What is the standard procedure to describe a circuit which is repeatation of small units(like the multiplier). I think we can use the "for" loop for that (i used the same in my design). But it can be included only in the always blocks ?? is there any other way for that? IS there any other way in which we can simply specify the connections as is done in schematic editor ?? regards sumesh

Reply to
vssumesh

Arrays of instances can only be 1-dimensional in Verilog. You can always map a multi-dimensional array into a 1-dimensional array anyway. Alternately, you could instantiate an array of instances, each of which handles an entire row by instantiating an array of instances to handle the individual elements.

Verilog-1995 only supported 1-dimensional arrays of data words also. Multi-dimensional arrays were only added in Verilog-2001. Multi-dimensional arrays of instances were probably not added because attention was focused on adding the more general generate constructs to do the same kind of things, rather than extending arrays of instances.

Reply to
sharp

Thanks for the suggestion. I am experimenting with the generate key word. But while doing that some problem observed. the following code gave error. "index out of range".

for(i = 0; i

Reply to
vssumesh

This may only be a warning, since the behavior is perfectly well defined in Verilog. And since the C[i-1] part is thrown away when i was zero, it really doesn't matter. However, perhaps your tool is being extra strict.

Well, you could keep the index in range in the i==0 case also, even though you are throwing it away, with something like

assign A[i] = (i!=0)?B[i]&C[(i!=0)?(i-1):0]:1;

Or you could put a generate-if inside the generate-for-loop:

for(i=0; i

Reply to
sharp

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