model sim block ram sim

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Hi -

I am trying to run a very simple simulation to verify the functionality of
the "block ram" component in my spartan ii fpga.  I am using modelsim
tools that I downloaded from the xilinx website, and I'm using the
"ramb4_s8" primitive.  The simulation appears to work properly except that
there appears to be a delay of one clock cycle when reading from the
memory.  In other words, if I enable the ram, deassert the write enable,
and select the read address, I need TWO rising clock edges to get the
correct data to appear at the data_out port.  I am doing a simple
behavioral simulation so there shouldn't be any delay issues involved.
The data sheet clearly shows that I should only need one rising clock edge
to execute the read.  Any ideas?  Thanks very much!!!

--Iyad

-------------------------------
Iyad Obeid
Dept. of Biomedical Engineering
Duke University
snipped-for-privacy@duke.edu
(919)660-5104   www.duke.edu/~io

Re: model sim block ram sim
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Maybe you need to register the address.
http://groups.google.com/groups?q=sync_ram+entity+lpm_ram_dq

  -- Mike Treseler


Re: model sim block ram sim
In Virtex BlockRAMs nothing happens without being instigated by a clock
edge. That's why they are called synchronous RAMs.
Peter Alfke

Jim Wu wrote:
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