Hi -
I am trying to run a very simple simulation to verify the functionality of the "block ram" component in my spartan ii fpga. I am using modelsim tools that I downloaded from the xilinx website, and I'm using the "ramb4_s8" primitive. The simulation appears to work properly except that there appears to be a delay of one clock cycle when reading from the memory. In other words, if I enable the ram, deassert the write enable, and select the read address, I need TWO rising clock edges to get the correct data to appear at the data_out port. I am doing a simple behavioral simulation so there shouldn't be any delay issues involved. The data sheet clearly shows that I should only need one rising clock edge to execute the read. Any ideas? Thanks very much!!!
--Iyad
------------------------------- Iyad Obeid Dept. of Biomedical Engineering Duke University snipped-for-privacy@duke.edu (919)660-5104