ML501 Constraints file problems

Hello,

I'm testing ML501 board, very nice. On the Xilinx site the documentation of this board has some errors like the constraints file(...also unavailable...).

Looking the EDK example design I see errors between UCF file generated for "ml501_bsb_design" and the Schematics(Sheet 3 of 22, for example)

All DDR2 memory pin connected to the FPGA Banks are wrong(they are inverted?)

I rebuild from scratch pin-to-pin from the Official schematics all DDR2 LOC pins to implement one working UCF file but I found this incongruence in the EDK UCF file.

What UCF file I use with this Board?

Reading this simple guide I made a bitstream without problems, and It's working well.

In this situation I think the UCF file generated by the EDK flow are ok However I think there's a confusion.

I think is a good idea if Xilinx put a general UCF file for her ML501 board with DDR2,ETH,USB, and other constraints to safe lot of time(with a lamp and zoom into schematics....).

happy day, Callisto.