ML403 dcm phase shift reference design... anyone has a copy ?

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I'm trying to play with the OPB MCH DDR controller (multichannel ddr
controller) on Microblaze platform, on S3.

Unfortunately, I have no example to start with. Even on Xilinx site I found
not so much help.

I saw on the ML403 user guide that with that board comes an example:


that seems to fit.  Even if the ML403 is Virtex 4-FX based, this design uses
a Microblaze.

I don't really know if asking for a copy of this to some kind people is a
copyright violation; I own a full license of EDK, ISE, and a Memec demo
board, but no really useful examples to start.  I'm just asking for a little
help to make me purchase more chips, sooner :-)

I would prefer not to have to purchase the V4-FX board, because my design
will be S3 based, and my board already has DDR.

Can anyone help ?

Meanwhile, I'll ask my FAE, but with the Memec / Avnet fusion still to
settle, now it's not a good period to ask for help...

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