Dear friends,
I'm a novice and playing with Xilinx ISE Webpack and ModelsimXE. I have a 'TOP' Verilog module in which I have instanced 2 module: 'A' and 'B'; I have a testbench for 'TOP' and want to simulate with 'A' sinthesized and 'B' not synthesized ('B' is not synthesizable; it has for example '#...' statement). Is this possible ? How ?
Thanks and Regards
Silvano