Hello,
I have a newbie problem that is probably easy to solve.
I have 4 data streams entering Virtex II FPGA through LVDS standard (each stream is 4 wires, 2 clock and 2 data). This is fine as I am able to receive the signals each individually i.e. data from each stream is clock by only their respective clock and the data does not interact with each other.
What I want to do is to treat each stream as a bit of a word i.e. have them all clocked by a single clock. Because these streams are independent clock phases and probably clock jitter is not equal, though frequency should nominally be equal.
Is there a way to generate a single clock and/or correct for phase differences on the data streams so that can can treat the data as a single "word"? How should I look at this problem?
Herwin