Hi. Quick question for you all.
I have a 20MHz FPGA clock and I have some very low frequency periodic actions to take care of so I want to generate an approximate 10Hz clock to give to the modules that need it so they don't need their own big wide counters.
module slowclk(input clk, output slowclk); reg [19:0] cnt = 29'h0;
assign slowclk = cnt[19];
always @(posedge clk) cnt