Hallo to everyone, I should develop a system which outputs a pwm signal into a filter to obtain a sine at 500 Hz which will command a class D amplifier.
I was considering to use dds compiler to generate digital sine, then putting the output in a pwm generator, like the one seen in fpga4fun website.
If I can't use a high frequency oscillator for fpga, because of the limit of class D amplifier, may I use an oscillator of 500kHz about?
Generating a "digital sine wave" requires a clock frequency higher than the output waveform. The clock oscillator for the FPGA can be at many MHz, allowing the sine wave to have many samples per waveform period. This is how you get a smooth wave without resorting to a very tight low-pass filter on the output.
You can also create the PWM waveform inside the FPGA, which would remove your analog filtering requirements on the sine wave, but would require an even higher clock frequency to achieve a reasonable duty cycle resolution. The frequency limit of the class D amplifier is only on the output frequency of the PWM, not the oversampling clock used to generate the waveform.
You are right that DCMs have minimum clock freq restrictions (eg 24MHz in V5), but not sure why you want to use a DCM. You are not trying to phase lock to the input clock source or multiply it up so you could just use the low skew clock resources in your FPGA to pipe the clock around. You could use standard counter (eg a LFSR) to divide down your clock.
Hi Dunstan, Indeed, he is right, but I think you may not be. To be technically correct, (the best kind of correct!) if you use only the DFS output, FCLKINLFFXMSMIN is 1 MHz. Read DS202, tables 50, 51. I couldn't find 24MHz anywhere, are you thinking of a different family? V5 MS mode apparently has a minimum of 32MHz, MR mode
My aim is to create an output from one fpga pin which will be a pwm sine. This signal will be amplified using a class D amplifier to obtain a 200 Volt with 3 amperes output, so if minimum high time of that signal is 50ns (considering a 50% duty cycle of a 10MHz clock), and the transistor of amplifier have lower band, in which way may I amplify that signal?
I don't know power amplifiers, but I think that 10 MHz switching it's very very high.
Marco, You may use the FPGA to create a square wave in a fixed frequency (say
50KHz) and variable duty cycle. This duty cycle variation you do using a counter and the step it changes will be your resolution. If you use a 10MHz clock in the counter you can get up to 199 steps. A 50MHz clock would give you near 10bits. Use a table (like a BlockRAM - in Spartan3 family you get a 1Kx16 RAM that you can innitialize and read as a ROM) to output the dutycycle variation in order to shape your sine. Now, use a filter (Bessel or other - even a RC filter can give you good results in your first try) to get the energy on every square wave translated to a voltage. The fixed base frequency helps to tune the filter precisely and get a higher resolution. In order to get a correct Vpp in the filter's output (as well as a lower impedance) you may have to use an Operational Amplifier such as LF347 type. The output of the filter you will inject in your amplifier. Don't forget you may need an AC coupling to the amplifier and you can get it using a simple electrolitic capacitor between the filter and amplifier's input.
Of course, the rate you read the table will be the rate the voltage changes in the output, giving you the frequency of the generated signal. In order to reduce distortion you must keep the reading rate less than the square wave frequency. In the given example you cannot read faster than 50KHz. For a 64 point sine wave and reading the table at 49.9KHz gives you 779,69Hz in the output. If you want a 500Hz signal with 128 points you must read at 64KHz. So, you can reduce the precision of the sine wave to less than 100 points or increase the square wave frequency to over 64KHz.
This means the PWM will have a frequency of Fs =3D 250 kHz which is a =
period Ts =3D 4 us. On each PWM period, the output will be high for a certain time T, and l= ow =
for the rest of the period, or Ts-T.
So, first, you need a digital sinewave, that is a sequence of digital =
samples, with a sampling frequency Fs. Then, for each digital sample, you set the output PWM signal to 1 for a= =
time proportional to the sample value, and then to 0 for the rest of the= =
period.
You could implement it with a DDS (to generate the sine samples) which = =
outputs a sample every Ts. Every time a sample is produced, - the PWM output is set to 1. - and a counter is set to the value of the sample. Then using a main clock, of frequency Fc, you decrement this counter. =
When it reaches 0, you set the PWM output to 0.
This will give you your PWM signal. Now, which frequency to use for the main clock Fc ? This depends on the= =
precision you need. With a faster clock, you will be able to cut the Ts = =
period into smaller slices and your samples can have more bits. Let's suppose you use Fc =3D 50 MHz which should be perfect for a Spart= an-3. In this case every sample Ts (4 us) contains 200 cycles of your main =
clock.
Therefore, your sine samples should be between 0 and 200 (integer). You= =
can use a 8 bit counter. Now using the minimum and maximum duty cycle specs of your class-D amp,= =
you can determine that your sine samples should be between 2% and 98% of= =
200, this means 4 and 196. You need to set those parameters in your DDS.=
=
I think you were confused because there are several clocks here : - the main clock which drives the counter which sets the duty cycle of = =
the PWM (in this case 50 MHz) - the sample clock (in this case 250 kHz) - the output PWM signal frequency (in this case 250 kHz too)
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