minimum module name length in 6.3i?

I have a design that has compiled fine under ISE for three years. Now ISE

6.3i sp2 has a problem with the module name "adc". Specifically, it can't figure out this module's correct place in the design hierarchy. In the "Sources in Project" window it lists this module at the top of the hierarchy instead of down under the module in which it is instantiated.

Adding one character to the module name fixes the problem. Anyone else seen this? The problem did not exist in ISE 5.2i sp3. That's the last version I used before 6.3i sp2.

Rob

Reply to
RobJ
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Well I have modules named "cpu" and "alu" under 6.2... I wonder if I should upgrade ;-)

Have you tried other three letter combinations? Could it be a reserved word problem rather than a minimum length one?

Reply to
Chris Stratton

That might make some sense. I belive the new Virtex 4 that is supported under 6.3 has an internal ADC. Seems like a bad choice of names to start restricting though. This might be a bug.

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Rick "rickman" Collins

rick.collins@XYarius.com
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Reply to
rickman

No, I didn't think of that. Changing from 'adc' to 'adc1' fixed it, but I ended up calling it 'adc_if'. I kind of doubt it's a reserved word problem because it did pull the module into the project. It just put it in the wrong place. I'll open a case with Xilinx when I get a minute.

Rob

Reply to
RobJ

Just a wild guess, I experienced a similar problem when I used the xilinx core generator. it went like this - I created a XCO module using the core-gen tool and inserted it to the project. afterwards when I wanted to create a new project I copied all the files from the old project but insted of taking the xco file I took the .vhd file (that was also generated by the core gen tool) and attached it to the project instead of the .XCO - then the project view gave me the picture you described. So maybe if you are using core gen modules you can check out this option...

Regards, Moti.

Reply to
Moti Cohen

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