Minimum allowed clock frequency for Nios 2 processor (Stratix 2)

Hi,

I wanted to know if there is any lower limit on the minimum possible clock frequency that can be given to a Nios 2 processor. The Stratix 2 board has a 50 Mhz clock which also drives the Nios2. But I want to run the processor much slower, in Khz range. Can I go on reducing frequency? The board also contains some offchip SRAM and SDRAM, whic Nios2 can access. Will the frequecy be limited by the clock given to SDRAM ? TIA Sunny

Reply to
Sunny
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I dont believe that there are any minimum clock frequency. Though, you will propably find some practical challenges on your way.

  1. I don't think that you can drive the output frequency of the pll's down as far as you want. You can propably splve this by using a clock divider circut, feeding the result back to the global clock networks.

  1. I would expect some timing problems with the interface to circuits like the SDRAM, but nothing that can not be solved.

So the simple answer is: Go ahead and try!

Havard

Reply to
htoerrin

The Nios 2 itself, and all surrounding logic, should run at any speed up to the maximum for the design. As long as a design does not rely on timing delays (and a good design should not, obviously), there should be no problem clocking it all with an external toggle switch.

The SDRAM, on the other hand, will be a problem - data is stored in tiny capacitors, and needs to be refreshed at regular intervals or it will leak. As you lower the clock speed, there is less time (i.e., fewer clock cycles) between refreshes, until you can't do anything with it but refreshes. Lower than that, the SDRAM is useless.

PLLs also have limits on their frequency range - you just have to add divider logic to reduce the clock further.

Reply to
David Brown

I think there was a similar discussion on

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. The problem was that the JTAG-UART (for debugging) did no longer work a low frequencies (I think it was around 10MHz).

The SDRAM will not operate successfully at these low frequencies as others mentioned. I think, with the latest Nios-version it is possible to use a different clock for the SDRAM than for the Nios.

But why do you want to operate the Nios that slow? (If it is for power-reduction, I think you should not choose a Nios-solution anyway...)

Regards

Thomas

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Reply to
Thomas Entner

As far as I know, the lower frequency limit applies to the PLL. So when you don't use the PLL, you should be able to go down to DC.

Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
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Reply to
Rene Tschaggelar

Hi Thomas, Thanks for your reply. The reason I want to slow processor clock frequency is that I basically want to stop the processor from executing when I want, and give it clocks only when needed (through some clock gating mechanism). It is a multiprocessor system where one processor will run at high speeds (~50 Mhz) and the other processor will run only when needed. So I wanted to know if can the processor retain its state for an indefinite time? I will take care of SDRAM clocks separately. Some processors like Pentium have a specification for the lowest clock frequency because they cannot retain the state for long enough (due to capacitors getting discharged). Is there any such limitation for Nios 2 ( essentially the FPGA fabric) ? So what I am looking for is that clock period should be theoretically infinite.

For JTAG - UART can you direct me to some place where I can read exactly how it works and why debugging fails below 10Mhz.

Thanks Sunny

Reply to
Sunny

Hi Sunny,

some links:

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(this is the thread I mentioned)

Beside these (and the SDRAM) issues I see no reason why the Nios-core should not work even when the clock pauses for a long time. Of course you should take great care that the clock-gating does not introduce short glitches as these would cause troubles. Also peripherals like UARTs, etc. will behave incorrectly when the clock is stopped during operation.

Regards,

Thomas

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Reply to
Thomas Entner

Hi Sunny,

Others have covered the main things to watch out for here. There is one more: If you want to consider stopping the clock entirely to a CPU or set of CPUs, you should consider having them jump to some sort of sleep routine that will spin until woken up. The reason is that you don't want the processor to attempt a memory or peripheral access when it is sleeping, as this will essentially 'lock' access to the slave in question (which could possibly be acceptable depending on your system, but if you have shared memory and not all processors are 'turned off' it can be bad news). Obviously you'll either need an instruction cache (and a cycle through the sleep loop to get that code cached) so that no memory access is initiated.

About JTAG: The Tck frequencies vary by the cable that you're using. I believe the USB Blaster is fastest with a 10MHz Tck (this is from memory, not a datasheet). The JTAG UART and Nios debug core logic were built with the assumption that the CPU clock is running more quickly. Obviously if you do not want to debug or use the JTAG UART this won't be a consideration.

Jesse Kempa Altera jkempa -at- altera -dot- com

Reply to
kempaj

hi havard, thanks for the tips!!

Reply to
Sunny

hi jesse, If I gate the CPU clock it won't be able to execute any instructions. So it cannot access any memory or peripheral also. I didn't understand why it should go to sleep routine. Can you elaborate. Thanks sunny

Reply to
Sunny

hi david, I found that altera provides some sort of clock control block which may be useful for me. thanks

Reply to
Sunny

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