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Minimal pins for JTAG configuration

Hi,

I built a PCB with a spartan3-xc3s400 TQ144 and tried configuring it with the simple JTAG parallal cabel III from xilinx

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but ISE9.1 couldn't identify the FPGA. Since I soldered the FPGA myself, I think some pins are not soldered well to their pads. I need to know the minimal pins needed to make an FPGA configuration by JTAG possible so that I don't have to check all 144 pins. According to what I understood from the datasheet, the only pins needed to be connected to make the confguration and verfication through JTAG possible are:

TDI: Pin 144 TDO: Pin 109 TCK: Pin 110 TMS: Pin 111 and All GND's and VCCAUX's in Bank 0 and BANK 1 ( the Banks which the JTAG pins are connected to)

I am right here or wrong?

Thank You, JJ

Reply to
jidan1
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JJ,

You also need power and ground for the core voltage, Vccint.

And, you need Vcco for the bank that has the IO pins for the MODE selection, and configuration (even if these are unused, we still need to power the bank so the part will come out of reset and power ON).

The power ON reset requires: Vccaux, Vccint, and Vcco (on the config bank) before the part is allowed to do anything at all.

Austin

Reply to
Austin Lesea

Aha, I see...thanks for the reply. Another thing, according to the datasheet the power suplies to each edge (there are 4 edges and each edge has 2 banks) of the TQ144 are connected internally together, i.e. Bank0&1, Bank2&3, etc. Each edge has 3xVCCO, 2xVCCAUX, 2xVCCINT, 4xGND. Does that mean I need to connect ONLY one pin of each power supply per edge for the FPGA to function (since they are connected internally)?

JJ

Reply to
jidan1

JJ,

Yes, that would be true.

With only one power pin being shared, I would not expect the part to work well when a configuration is downloaded, but for JTAG, that is all that would be needed.

Austin

Reply to
Austin Lesea

With a multimeter I checked if the necesserly power supply pins and configuration pins are connected to their pads and they seem to be so. However, I might have accidently connected the pins to the pads by just pressing the pins with the multimeter probe or (worst case) the FPGA might be damaged. If the necesserly power supplies for configuration are not all connected, the POR( Power-On Reset) is activated. Is there way to test if the POR is activated or not from outside?

Reply to
jidan1

JJ,

If the part is connected properly, you will see the proper signal on INIT_B.

INIT_B will go high while the devices cleans out, and gets ready to try to configure, and then it will go low when cleanout is done before it starts to configure. If there is no configuration device present, then this sequence of INIT_B lets you know that the device is ready and waiting.

Also, if a master mode is selected, the CCLK pin should be running.

See page 56 of 280:

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Austin

Reply to
Austin Lesea

Thank you Austin for your help. I finally got to program the FPGA. The problem was on the programmer I used: Xilinx Parallel Cable 3. The strange problem with this cable has haunted me since I built it. I described the problem here:

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JJ

Reply to
jidan1

JJ,

Sounds like you have a signal integrity problem with the cable and the interface.

I suggest using Hyperlynx from Mentor to troubleshoot, or read up on SI.

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Austin

Reply to
Austin Lesea

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