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Re: "Mine is bigger than yours..."
Hi Peter,

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I believe that there is a fair bit of literature explaining where the
multiplier comes from.  Perhaps you (and others) do not believe the Stratix
II vs. Virtex-4 comparison.  However, we also have data on Stratix II vs.
Stratix utilizaiton showing ~25% higher utilization than you would expect
from straight LUT/FF counting.  I certainly hope we are capable of measuring
our own chips.  And previous (Altera-published) results showed that Stratix
I achieves a higher logic density than Virtex-2.   So the 1.3 multiplier is
at least consistant with other results.

Here is a link to a white-paper comparing Stratix II and Virtex-4 logic
densities.  http://www.altera.com/literature/wp/wpstxiixlnx.pdf .  And here
is another white paper on the ALM
http://www.altera.com/literature/wp/wpstxiiple.pdf .

There are also two academic papers published in respected, referred FPGA
conferences.  Both are authored by individuals who have established
reputations in the FPGA industry.  The first paper describes the Stratix II
architecture, including a section on the ALM (Lewis et al, "The Stratix II
logic and routing architecture", Proceedings of the 2005 ACM/SIGDA 13th
international symposium on FPGAs --  
http://www.eecg.toronto.edu/~jayar/pubs/lewis/lewisfpga05.pdf ).  The second
is specifically on the ALM (M. Hutton et al, "Improving FPGA performance and
area using an adaptive logic module", International Conference on
Field-Programmable Logic and Applications 2004).

The short version is that Adaptive Logic Module (ALM) can do 2 4-LUTs (like
a Slice or 2 Stratix LEs), but also can do a 5-LUT + 3-LUT, 6-LUT, and other
more powerful combinations (such as 2 6-LUTs that share 4 inputs, etc).
When you technology map a design into a specific look-up table (LUT) size,
you get a variety of LUT sizes -- you can't map all the logic to use exactly
4-inputs (for example).  Since you have a distribution of LUT sizes, the
capability to pair more than just 2 4-LUTs into a single ALM will result in
a decrease in the number of ALMs required.

Regards,

Paul Leventis
Altera Corp.

P.S. Ours is bigger -- and we can use it better too!



Re: "Mine is bigger than yours..."

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Well then when are you guys going to have a low cost board
similar to the spartan3 (or 3e) starter kit ?




Re: "Mine is bigger than yours..."
Hi Alex,

There are two Cyclone kits sold by partners of ours that are in the
same price range:

Future $49 Cyclone/Nios II eval kit:
http://www.altera.com/products/devkits/partners/kit-future-badge.html
Altium $99 kit:
http://www.altera.com/products/devkits/partners/kit-alt-live-design.html

With Cyclone II now available, I can assure you there will be low-cost
Cyclone II dev kits available in the near future.  Sorry, but I can't
comment on exact dates.

Regards,

Paul Leventis
Altera Corp.


Re: "Mine is bigger than yours..."

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I have an Altium Altera board(and a xilinx one)
It doesn't come with any project file ready to use with Quartus
and you have to work out the connections as well.
Only annoyance is lack of config prom.

The lack of Quartus  project files means it is unsuitable for beginners
unless
they are using it with the Altium software.

That future board is not even in the same league as the Spartan 3 starter
kit.



Alex



Re: "Mine is bigger than yours..."

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As a frequent Xilinx user (4K, Virtex-2, V2P, soon V4), I note that in the
slice (2 4-input LUTs), there is also available a 3-input LUT following
those two.  That LUT can be fed the input of [at least] one independent
input (besides the outputs from the two 4-input LUTs), creating the
opportunity to broaden the input set with minimal cost (delay, routing.)  I
have also extensively used the distributed RAM (sometimes as ROM), and
occasionally the SLR function.

I also have had occasion to use Altera, although not lately.  In '96 I had a
design where Altera had the appropriate solution (love those embedded block
RAMs, which Xilinx now has--features may vary), but in '97 I had a design
where Xilinx was better from a planning perspective (read:  growth path.)

Over the past 10+ years, I've had to get "under the hood" of the Xilinx
tools:  hand floorplanning, extensive timing constraints, reading lots of
app notes.  So you could say that I'm fairly comfortable with their
architecture(s) and tools.  However, I'd have to agree with some previous
posters:  if you think you have a challenging design, evaluate what you can
before committing.  That's what I have done in the past, and prefer to do in
the future (though usually, I'm stuck with a pre-determined selection.)
Typically, you can budget key resources (be that memory, LUTs, registers,
multipliers, pins, ...)   You can also do a test-case design that tests the
anticipated critical path.  The same principle applies for synthesis and
simulation tools, too.

Jason



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