"Mine is bigger than yours..."

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It's again time for the annual bragging frenzy, where every FPGA
manufacturer claims to have the biggest.

It seems so simple:
The Xilinx XC4VLX200 has 178,176 LUTs + associated flip-flops,
while the Altera EP2S180 has 143,520 ALUTs + flip-flops.
The conclusion is obvious, isn't it?

But this is not that simple. In the world of creative marketing,
everyone can claim to be the winner.

First Xilinx muddies the water by adding 12.5% to the LUT count, to get
credit for various embellishments, bringing the XC4VLX200 to 200,448
"Logic Cells". Crashing through the 200 000 barrier...

But Altera cannot stand to be left behind. They get creative and apply
a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576
"equivalent LUTs", thus even bigger than the Xilinx behemoth.
Altera also claims superiority in multipliers and RAM bits, but forgets
that the cheaper XC4VSX55 or XC4FX140 are much better endowed with
those attributes.

It is so easy to ridicule this puerile bragging contest and its
Freudian fix on one specific aspect, while ignoring far more important
features. Unfortunately, some poor innocent person might actually get
fooled by it.   Too bad!

For a more entertaining story, click on
http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm

Peter Alfke, Xilinx Applications


Re: "Mine is bigger than yours..."

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One way to avoid being fooled is
to write portable code and run
a trial synthesis/route/STA
for all the contesting devices.


         -- Mike Treseler

Re: "Mine is bigger than yours..."
The conclusion clearly isn't obvious. Designs are not flip-flop
limited so counting flip-flops and assuming this somehow equates to a
customer experience is rather naive (though certainly convenient for an
architecture that isn't optimized for logic efficiency). Altera has
used our entire benchmark suite to validate the facts.

Realistically of course customers should check out their own designs.
No customer will ever find a real design that lines up with the 30%
larger Xilinx claim (comparing the biggest devices). Most will find the
2S180 a little larger than the LX200 based on logic and a whole lot
larger based on RAM and DSP resources.

And customers should also try to actually purchase these large devices
before making any decisions. Unfortunately the "vast" 90 nm
experience making small density Spartan-3 devices doesn't translate
to actually shipping high-density parts. While there are likely a few
LX200 or LX160 devices that have shipped, facts are that Altera sales
are greater on the 2S130 and 2S180 devices alone than the collective
sales of all Virtex-4 products. Altera's patented redundancy,
operational excellence, and strategy of sticking to a single fab
partner significantly reduce risk for customers who need guaranteed
delivery of high-density FPGAs.

Dave Greenfield
Altera Marketing

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important
get


Re: "Mine is bigger than yours..."
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Does anybody have any data on how much performance (space or time) you
can gain by hacking some nice pretty portable code to take advantage
of device specific features?

How much time does it take to "try it" if that includes a round
of manual placement?

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
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Re: "Mine is bigger than yours..."
I did a correlator for Stratix with 8 parallel MACs where the 2nd try
was better than the 1st by 3x fewer logic cells and 50% better fmax,
just by moving the accumulators and moving (not adding) pipelining.
That's probably pretty extreme, but without taking a close look at the
Stratix DSP block I don't think I would have realized it.

Depending on how you code barrel shifters on Stratix II you can get big
savings by using the ALM to its maximum capability. I'd love to find
lots of other functions that map really well into the ALM.

-- Pete


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you
my
unsolicited
addresses.


Re: "Mine is bigger than yours..."
I've had a similar experience with a V4sx55 design.  Trying to
synthesize from RTL code and achieve high performance takes a lot of
"pushing on a rope", is frequently broken by gratuitous changes in the
synthesis algorithm from version to version, and then often won't meet
timing without a heroic placement effort.  doing structural
instantiation gets me the performance in less overall time, but at the
price of a design that is not very portable.



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Re: "Mine is bigger than yours..."
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...



Indeed a nice Article !

I feel it failed to address two important points that I, as a
customer, also find very important:

1) When I send en email to a company that will be deeply involved
in my revenue stream as a supplier of parts and tools, I expect
them to be responsive. Every time I send an email to Xilinx
(regardless if it is sales, tech support, or marketing) I get a
reply within 24 hours (we are in a different time zone as well +9h).
Out of the dozen or so emails we sent to Altera in the last year++
exactly zero where replied to (we either lost the customers who
asked for Altera based solutions, or where able to convert them
to Xilxinx based solutions). To bad !

2) Look at this newsgroup. Peter and Austin are always there in
the front line, standing up for their company, taking the heat
and bs from an open public forum. Plus Xilinx makes it a point
to have additional experts peeking in the group and helping
out where needed. Any problem reported is discussed in the open
and solved. There is no under the rug filing or shutting up the
customers. I can download an errata or post to the newsgroup
and get open solutions. I can't say that I see a lot of that
from Altera. Yes Paul seems to be out there as well, taking on
a fight here and there. But I find there is a lack of discussion
level as with Xilinx. I know if I run in to a problem with Xilinx
devices, I can always turn to this news group and get help.

Just my two Euro-cent ...

Best Regards,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis



Re: "Mine is bigger than yours..."
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Rudi,

I don't think this point is quite fair. Besides Paul there are myself
(Nios/embedded questions here are what I answer), Vaughn, and others.
On the embedded side a lot of people have moved over to asking
questions on a new webaite (www.niosforum.com) where there area Altera
people from the engineering/apps/marketing teams who respond quite
regularly.

I won't comment on the original FPGA Journal article, other than to say
that I enjoyed it :) On the other hand, one should realize that X has
been playing the same marketing games for years now without a peep from
the press...

Jesse Kempa
Altera


Re: "Mine is bigger than yours..."
I have to agree. Jesse, Paul, Vaughn, and Subrotta (I'm sure there's
more) have responded quickly to things with Nios, Quartus, etc, from my
point of view. Take a look at how often, ie., Subrotto has responded to
problem designs in the past. I'm very thankful for their presence.

As for getting to people inside Altera, develop a good relationship
with the FAE and let them do that for you - it's worked for me.

-- Pete

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Altera
say
from


Re: "Mine is bigger than yours..."

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Jesse, Pete,

I did not intend to offend anybody. I am sure there are many
great guys here from both camps. My point was that I seem more
tough discussions in the Xilinx camp.

I don't know what the cause for that is. Are Altera user not
doing any (b)leading edge designs ? Are they not using any
fancy features of the devices, are they not pushing the devices
to the limit ? I don't know. It's just my personal observation ...

Regards,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

Re: "Mine is bigger than yours..."

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It might also be at least partly to do with the type of people
representing Xilinx and Altera in this newsgroup.  I get the impression
that certain Xilinx posters provoke discussions and arguements by their
enthusiastic or agressive (depending on your viewpoint) promotion of
Xilinx parts, while most Altera posters seem quieter, and will answer when
asked.  Both camps appear to have knowledgable and helpful posters,
although obviously you have to remember that sometimes their facts and
figures are seen from a biased viewpoint.

Having not used Xilinx devices, I've had no occasion to test Xilinx
support - but when I asked for help here for Altera devices, I got general
information here, more specific help in private emails, contact from my
FAE (obviously Altera people work closely with their FAEs), and in general
a lot of interesting and useful information.  The problem turned out to be
a typo in my code with bizarre side effects, but I was very happy with the
support I got.



Re: "Mine is bigger than yours..."
Rudi,

No offense taken at all. If you have any sort of Altera question you
think is suitable for the news group, feel free to ask here and I'd say
there is a good likelihood of it getting answered. I think David's
comment below reflects the personalities of the individuals from A & X
who post here pretty accurately.

On your other question about leading edge designs - the people who will
see this each day are the sales/FAE staff for each company. My
intuition and customer experience tells me that the competition is
fierce and both companies' products are used in leading edge designs in
all sorts of markets, but any more (from me) would be pure speculation.

Jesse Kempa
Altera


Re: "Mine is bigger than yours..."
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Hi Rudi,

there defenetly are bleading edge designg on Altera devices.
what might interest you is that the only really available low cost ($795)
FPGA PCIe board is based on Altera and not on Xilinx silicon.
Altera also claims that the Stratix-GX based PCIe solution passed
compliance testing in full. Thats of course BS as the Stratix-GX
has about the same amount of PCIe compliance issues as rocketIO/X (pre V4)
but the Stratix-GX can pass PCIe compliance on the PCIe plugfest even
if it is not fully compliant to the PCIe spec (those non compliance issues
dont actually matter in most real life applications). And as it has been
said here the new GX FPGA is coming too...

Antti



Re: "Mine is bigger than yours..."
Past:  I did a lot of leading edge (in terms of size) FPGA designs for
ASIC prototyping.   Size, usability, and cycle-time is of the essense.
In the past, I have used Orca (1996), Virtex , VirtexE,  and V2.  About
5 years ago, I looked at Altera and Quartus pretty much shot them in
the foot.

Current: In the new design, I once again evaluated state of the art
FPGAs.  For this cycle Virtex4's timeline was a little too late (by a
couple of months), so I started in StratixII (2S130s and 2S180s).  So
far, I have been very impressed with the tools and results.

Note: Altera's FPGA is not totally symmetric.  Different types of
memory, different type of PLLs, only certain PLLs can do feedback,
vertical I/Os are different than horizontal I/Os.  I thought this would
be difficult to keep straight.  However, I am getting to realize the
design I am working on is very not symmetric, so this has not been a
problem.

Memory:  I first thought that having to worry about the different types
of memory (512, 4K, 512K) was going to cause a accounting nightmare,
but you can actually set it to decide for you.   Quartus decides for
itself which one to use.  I really like this.

Synthesis: I have been impressed with the synthesis results.  Not as
good as Synplify Pro, but it comes with Quartus II.  We are having a
problem where Synplify is not finishing on one of the FPGAs and having
the Quartus synthesis engine saved us.  Also, synthesis in Quartus
takes about 2x-3x more computer time than synthesis in Synplify.

Physical Synthesis:  I was incredibly impressed with this since it is a
check box (vs. psuedo-floorplanning with Amplify or hand modification
with Precision).  For me, it is the difference between closing and not
closing timing.  One note though, some of my design grow by 20% when I
turn this on, so make sure you have a lot of head room.

Logic: I really like the ALM.  It does cut down on the number of levels
the logic has to go through.  This helps with timing.  Despite what
either Altera or Xilinx have to say, I really don't need a 1:1 ratio of
logic elements to FF.  About 10:1 ratio for ASIC prototyping is a
better ratio.  I would really like to see what other designers see.  I
would really like to see future families have at least 2x more logic
vs. FFs.

PLLs:  I like the analog PLLs vs. DPLLs of Xilinx.  One warning, if you
set QuartusII to decide the PLL type, you may not get to use all the
ratios.  Kind of bizarre, but that is the way I interpreted the tool.
I just set to only use Enhanced and the problem went away.

General: The tool flow is a little bit cleaner, but the Xilinx tool
flow was pretty good, so that is a wash.  I am not a tcl expert, so it
takes a little getting used to.  I do like when you finally get all the
tcl scripts right, you don't have to remember any switches, but once
again a wash.

Support: I am getting great support both locally and from the factory.
Of course your mileage will vary and may ultimately determine your
choice and your success.

Not used: I did not use processors, high speed transceivers, other IOs.


Cons 1: I was playing around with some different partition and I had a
design that was 85% full (in terms of logic) and Quartus II could no
route it at all (with no timing constraints).  To be fair, I have other
partitions with more than 90% that did route.  In previous Xilinx
devices in the Virtex* family, I only had problems closing time (i.e.
routing did not fail) at 95%, so budget your size appropriately.

Cons 2: Currently, there is no flash part that could program more than
1 of these large devices.  It really makes the JTAG chain on the board
needlessly complicated.

-Edwin


Re: "Mine is bigger than yours..."
Here is one more opinion from a person that only does FPGAs from time to
time. I guess that makes me a non-professional :) (The rest of the work
time is spent doing hardware design and writing code.)

Long time ago I was impressed by the Altera tools when I needed to do  a
simple CPLD, but found out that the A parts were much more difficult to
get than X parts. So I ended up using 95xx. Mostly for this historic
reason when it came to finding cheap FPGAs I have looked at the
Spartan 2/3 line first. The free picoblaze was a big bonus too.
Then I had to do another desing on a Cyclone and took another look at
the A tools. A number of pleasant surprises. I wish the two giants would
take the best features from the other one! So here is my list of great
thing in one that is not in the other in no particular order.

1. Quartus has a fantastic tool to do both built-in logic analysis and
modify the BRAM on the fly. ChipScope appears to be harder to use unless
I'm missing something. For example it won't work unless all the inputs
are connected to valid signals. No way to have spare inputs and do late
routing. No way to read/write BRAM unless you write a JTAG utility
yourself. Big plus to A.

2. Neat table view of the build results all in one place.
3. Timing results easier to track.

On the other hand:

1. No free CPU. Had to make my own: Nios may be great but one hell of an
overkill for my project.
2. Not enough BRAM in Cyclone. Does the Cyclone 2 exist outside the lab yet?
3. Very few development boards with A chips.

So that project done I'm mostly back in the X camp. Wish they could add
the memory access tool...

Re: "Mine is bigger than yours..."
Hi Alex,

Glad to hear you had a (mostly) postive Altera experience.  I've sent your
feedback on to the planning folks.  And if you need a CPLD in the future,
take a peak at Max II.

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Yes, Cyclone II is available.  The EP2C35 is shipping and the EP2C70 and
EP2C20 will be shipping very soon (May and June respectively according to
http://www.altera.com/products/devices/cyclone2/overview/cy2-overview.html ).
The product roll-out is going very well and devices are rolling out ahead of
schedule.

Regards,

Paul Leventis
Altera Corp.



Re: "Mine is bigger than yours..."
BTW, there are dev kits available for Cyclone II.  The DSP dev kit,
Cyclone II edition and the Nios II dev kit, Cyclone II edition (which
use an EP2C35) are now shipping. The PCI dev kit, Cyclone II edition
will start shipping next month. Customers can place orders for all
these today.

DSP: http://www.altera.com/products/devkits/altera/kit-dsp-2C35.html
Nios II:
http://www.altera.com/products/devkits/altera/kit-nios-2c35.html
PCI: http://www.altera.com/products/devkits/altera/kit-pci-2c35.html

Regards,

Paul Leventis
Altera Corp.


Re: "Mine is bigger than yours..."
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those all are WAY over priced compared to hpe-mini
http://www.trs-asic.com

Antti
PS Paul, I recently sent you an private email, just out of curiosity did you
receive it?



Re: "Mine is bigger than yours..."
Hi Edwin,

I'm glad you had a positive experience with Quartus and Stratix II.

I'm sorry to hear you got an unroute in one of your compiles though.  I'd
greatly appreciate it if you could send me the design, so my team can take a
crack at routing it.  We don't have very many unroutes these days, even at
very high logic utilization, so case studies like this are very useful for
improving our tools. We would use the design only to tune our tools, will
never release it outside Altera, and frankly we won't understand your design
as anything but a place and route problem instance anyway :).

It's most likely we can route it in house with more "routability tuned"
compiler settings, which we will send back to you as well.

Regards,

Vaughn Betz
[v b e t z (at) altera.com]



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Re: "Mine is bigger than yours..."

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Well, IMHO it is quite fair. The quality of support from
the Xilinx-associated experts is far better than from Altera.
A striking example: once I asked here about clocking
of the Cyclone 1C6 device (i.e. is it possible to use
a sine wave as a clock source of a PLL?). And it was
a Xilinx guy who gave me a comprehensive answer... :-)

    Best regards
    Piotr Wyderski


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