Hi all,
I have a signal that originates at a given device with known timing with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20 ns max.
This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed by the internal CPLD logic. So the timing after going through the CPLD relative to clock (clock does not go through the CPLD) would be like this:
tmin = 2 + min(CPLD prop. delay) ttyp = 8 + typ(CPLD prop. delay) tmax = 20 + max(CPLD prop. delay)
The Xilinx datasheet specifies propagation delay in this case and for this device to be 10 ns maximum in total, including input and output buffer delays. However no minimum or typical times are given.
I do understand typical times are of limited usefulness but minimum I'd need to know. Right now I can only take 0 ns as minimum but I assume there must be a better way.
Does anyone know whether this data is available in any of Xilinx's white papers or ANs (haven't found anything so far) or available on demand, or can anyone suggest what's the best way to handle this case?
Thanks, Guillermo Rodriguez