MII SFD Detection with Shematics

You could crosspost to comp.dcom.lans.ethernet.

Though there isn't so much traffic over there, it still seems like the right place.

-- glen

Thanks for the advice I will also try my luck there.

So for the question with the Schematic in generell. How do I check for Signals that are High for more than one Cylce. Something like: If Tx_En is asserted begin to check: Signal ( TxD0 & TxD2) == 1 for 16 Cylces Signal ( TxD1 ) == 0 for 16 Cycles Signal ( TxD3 ) == 0 for 15 Cycles and after that its rising to 1 output SFD detected!

If its not possible with logic from schematics I have to learn some verilog and vhdl :)

Thanks and greetings

that are High for more than one Cylce.

and vhdl :)

You'd use the same structures whether it's schematics or HDL. For each bit you need history of the most recent 16 cycles. This usually means you want a 16-bit serial-in parallel-out shift-register. Look for the desired bit patterns on the output of the S/R. This generally means a 16-bit AND gate with various inputs inverted. If this pattern could crop up unexpectedly during a data packet, you'd need some additional logic to filter it out. For that, a state machine may be better. There's nothing to say you can't have a schematic based design with state machines, but most people generally use HDL for that. When I was designing FPGA's with schematics, all of my state machines were HDL "macros" instantiated in the schematic.

-- Gabor

Ouch; state machines in schematics... that brings back some painful memories.

I usually used a ROM with feedback from Q to A. Some data bits were outputs. Some address bits were inputs.

I also occasionally used a state register that fed the control lines to a mux, whose outputs fed the state register. The inputs to the mux defined next state and any outputs.

HDL is SO much easier...

Andy

Interesting, I can't imagine designing state machines in anything else but schematics ;-)

I use HDL Designer to quickly draw a bubble diagram and let the tool generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine, sync/async reset, encoding style, etc.).

Hans

Some address bits were inputs.

whose outputs fed the state register. The inputs to the mux defined next state and any outputs.

There are state machine design tools, but the usual meaning of schematic is you move gates and registers around, then connect the inputs and outputs with lines. Be careful that the lines aren't on top of previous ones, where they might accidentally connect. (Some editors make such accidents easier than others.)

Fortunately I never did that before learning verilog. I did some for other projects after using verilog, though. I find it much easier to hand convert to verilog than to work on something in the schematic editor.

-- glen

Huh? Real electrical schematics? Are you sure?

Oh, the state machine designer. Yes, that actually works, up to about

20 states. When you get up there, the page becomes VERY unwieldy, and the self-documenting concept kind of falls apart. I tried it, ONCE, and decided that:

if state = x1 then if y=z then state = x2

works a lot better.

Jon

Sorry, but bubble diagrams of state machines drawn in HDL Designer are not schematics!

I would like a tool that converts HDL into a re-arrangeable graphical bubble diagram (they never seem to arrange the diagram the way I intended it) for documentation.

HDL source is portable and maintainable long after HDL Designer is obsolete, license expired, etc. And the machine-generated HDL source code is rarely very human readable.

Andy