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Migrating to Actel Libero

Hello all. I am trying to migrate from Xilinx ISE to Actel Libero. I created a new project in Libero and copied the *.vhd files from the ISE project. Then I replaced all the Xilinx FIFOs and CLKDLLs with the equivalent Libero specific cores. When I tried to synthesize the project using Synplify Pro, I obtained the following error message. "Can't open input file C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd" I am not using any Unisim components in the Actel Libero project. Then what cause can result in this error.

Thank you.

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Reply to
matrix
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Are you sure that you have no usage of library unisim in any file? Try searching for "library unisim" in all hdl files. I guess that Synplify has some build in mechanismes to check under /xilinx if unisim or simprim is used in design. But actually I'm surprised that even the Actelversion of Synplify has this build in.

bye Thomas

Reply to
Thomas Stanka

You may have replaced any such components, but it is possible that some source files still contain (now unnecessary) library clauses, referencing the unisim library.

- Brian

Reply to
Brian Drummond

C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\xilinx\unisim.vhd"

Solved. One of the source files contained a library initialization for unisim, as Thomas and Brian had pointed out. Removed that clause and the error message disappeared.

Thank you all.

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matrix

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