Hello all, I am creating at MIG a external DDR2 Memory controller. Then i am trying to add this core to an XPS design. This controller i want to be attached at the PLB bus. When i am going to import peripheral from XPS my created core signals does not interface in total number with the PLB's ones.
I would like to ask if there is a PDF or something similar explains the step by step the process for core insertion from coregen to an XPS project.
regards xenix