micron sdram module

That should be easy to determine from the source code. The data is stored in the variables Bank0-3. But if you can cosimulate with Verilog, I would suggest using the Verilog model. It is more up to date, though judging by the change log the changes are relatively minor. But a big advantage is that it prints out reads and writes, including the address and contents. Though in some situations that might be considered a disadvantage.

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My real email is akamail.com@dclark (or something like that).

Steven,

I have a similar problem in that I have downloaded a SDRAM VHDL module from the Micron website and have developed a master peripheral to the Avalon Bus using SOPC Builder in Quartus. In this, I merely connect to the SDRAM controller which is physically connected to a

128Mbit Micron SDRAM. When attempting to simulate this SOPC design interfaced directly to the SDRAM module from Micron, I don't manage to see any of the data that I have put in the WRITE phase, as when I do a READ I get crap out. The verilog doesn't work well as I have not managed to be able to interface Verilog and VHDL properly within the same design. Definitley my lack of experience in this area to doing it correctly. So perhaps this is a similar issue, but I am unclear what the MICRON module is supposed to do as I don't see anything coming out? Is the module supposed to retain information and return it on the bus when you request it (i.e a READ)?

REgards, Pino

if you are writing to SDRAM module you can check value written at lines: ...

-- Write back to memory IF Bank = "00" THEN Bank0 (Row_index) (Col_index) := Dq_temp; ELSIF Bank = "01" THEN Bank1 (Row_index) (Col_index) := Dq_temp; ELSIF Bank = "10" THEN Bank2 (Row_index) (Col_index) := Dq_temp; ELSIF Bank = "11" THEN Bank3 (Row_index) (Col_index) := Dq_temp; END IF; ....

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and if you read you may check: ... ELSIF Data_out_enable = '1' THEN IF Dqm_reg0 /= "1111" THEN -- Initialize memory Init_mem (Bank, Row_index); -- Load memory into buffer IF Bank = "00" THEN Dq_temp := Bank0 (Row_index) (Col_index); ELSIF Bank = "01" THEN Dq_temp := Bank1 (Row_index) (Col_index); ELSIF Bank = "10" THEN Dq_temp := Bank2 (Row_index) (Col_index); ELSIF Bank = "11" THEN Dq_temp := Bank3 (Row_index) (Col_index); END IF; ...

in micron VHDL SDRAM simulation model (example for quad bank 64Mb Micron model) I've designed simple sdram controller with testbench instantiating Micron SDRAM 32Mx2 model, you can check it at

Mike

Thanks, Duane. It is quite obviously that Bank0-3 hold the memory contents. :) It is too large to put in the watch list. 64MB or more of each bank. Anyway thanks. The other tip from you is great, verilog module gives more info. Maybe micron also do not like old europe so they do not include such useful output in vhdl module. :)

Yes, Pino. The module works like physical module, only for simulation. It executes Read/Write command from your sdram controller, and holds the contents.

There is nothing special required for Modelsim, though I can't say about other simulators. You just instantiate a Verilog module as if it were a VHDL entity: -- MICRON DDR SDRAM Simulation Model MEM1 : entity micron.ddr port map ( dq => DDR_DQ(0 to 15), dqs => DDR_DQS(0 to 1), addr => DDR_Addr, ba => DDR_BankAddr, clk => DDR_Clk, clk_n => DDR_Clkn, cke => DDR_CKE, cs_n => DDR_CSn, ras_n => DDR_RASn, cas_n => DDR_CASn, we_n => DDR_WEn, dm => DDR_DM(0 to 1) );

--
My real email is akamail.com@dclark (or something like that).