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Microblaze LMB bus

Hi

Does microblaze do all the LMB transfers synchronously (ie, it doesnt support variable latency). If so, why is there a ready signal. If not, how can the second transfer be performed back to back without looking at the ready signal (as shown in the reference guide)?

Is there another bus which supports variable latency (OPB?? where is its timing diagram documented? )

Thanks Murali

Reply to
Murali
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You have not mentioned what exactly you are trying to do. Depending on what you want, the FSL or the OPB bus might be appropriate. The documentation for both of them should be available along with EDK.

/Siva

Reply to
Siva Velusamy

I am trying to connect a variable latency memory to microblaze. I would like to use the LMB bus since the interface looks simple. But from the timing diagrams in the reference guide, it looks like the ready signal is not used in microblaze. I just want to clarify that - whether the microblaze LMB interface is a synchronous (read non variable-latency) interface, which doesnt look at the ready signal in the bus.

Thanks Murali

Reply to
Murali

I'm not sure about the details of the LMB bus. Maybe someone else would comment on that.

Personally I think you should be using XCL if you want to connect a memory core to MicroBlaze. The XCL connection feeds into the caches of MB. Interface-wise, its extremely simple - an FSL bus with some protocol on top of it. You could look at any of the mch_* memcons in EDK.

/Siva

Reply to
Siva Velusamy

I dont want to use microblaze's caches, atleast for now. Thats why I am not using XCL. I want microblaze to be oblivious of how I manage memory.

Reply to
Muralidaran Vijayaraghavan

I finally checked what happens when using an LMB with microblaze. Looks like it is waits for a ready in the bus as the programs hang if they contain a load/store. So now my question is: how does the microblaze issue the next load/store when the first is in flight (according to the timing diagram in the spec). Does it issue a maximum of two instructions before looking at the ready? Checking this involves more work, so I would be happier if someone knows and can tell :)

Thanks Murali

Reply to
Muralidaran Vijayaraghavan

Hi,

The way uses MicroBlaze is different on the instruction side compared to the data side, at least for v4. For v5 the usage is the same.

V4 instruction side. MicroBlaze will just send out the address on one clock cycle and the next address will come directly after independent if there is a ready or not. Normally this is called overlapped address and data phases on the bus. When the LMb slave returns the ready signal, Microblaze will combinatorial drive a new Adress strobe. The new address is already on the bus as explain above.

V4 Data side. MicroBlaze will on recieving the ready signal NOT combinatorial drive the new address strobe but that will happen the nextr clock cycle. The address and data phase do not overlapped.

On V5, the instruction side and data side is the same and they uses the same protocol as the V4 instruction side.

The reason for this behaviour is due to the internal pipeline which differ from v4 to v5.

Göran Bilski

Reply to
Göran Bilski

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