MicroBlaze is no available as Open-Source!! (from independant 3rd party)

If you check out the syn directory in that archive it lists the sythesis results for various FPGA's. What is interesting is the frequency of operation in a Xilinx device is >3X the Altera device.

I would be very interested to see the results of a Nios-II core in a Xilinx Device!!

Hi All

finally today the project maintainer at opencores uploaded the verilog design files for MicroBlaze compliant IP-Core. Download is available at opencores.com - as project aeMB !!

for PicoBlaze there are 2 different open source 3rd party implementations known, i wonder when first NIOS-II open source IP-core will be available :)

Antti xilinx.openchip.org

get the archive, the verilog source is inside there, checked :)

Antti

How long before Xilinx try to get them to remove it do we reckon?

Cheers, Jon

Why do you think, they should ?

That doesn't suprise me at all. Each vendor has designed their CPU from the ground up knowing exactly how to optimize the design for their architecture. I am sure every little nit was used to optimize the design for speed and size. I expect the xxxxBlaze designs use a lot more LUTs in the Altera parts too!

As you say, it will be interesting to see how the Nios-II core fits into a Spartan-3. I will also be interested in seeing how it fits an Altera ACEX which Altera is not supporting with this design.

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If you look closer you'll see that the Altera devices used are pretty old...

Petter

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Very old. In this case, the best Altera part used is an EP20K100TC144-3 -- an original APEX 20K part, in the slowest speed grade. That product was manufactured at 0.25u technology. It is being compared to a XC2V80CS144-6, which IIRC is a 0.15u/0.13u hybrid, and is the fastest available Virtex-II speed grade to boot.

QUICK REMINDER: Altera numbers speed grades such that lower = faster. Xilinx numbers things so higher = faster.

Also, I should point out that the reported speeds appear to be based on synthesis estimates -- you really need to run place & route before you can ever compare results between two architectures. Synthesis performance estimates give you a reasonable idea of how changes in a given design affect its performance, and they *should* be tuned to give the right answer on average over a large set of designs. But on any given design there's no guarantee the estimate will be close to the final P&R value, and there are both systematic design-specific and completely random components to this error. In short, comparing post-synthesis Fmax across two chips on one design is quite inaccurate.

As other users have pointed out, this core may also be optimized towards Xilinx like architectures. I have not looked at it and thus do not know if this is the case.

Regards,

Paul Leventis Altera Corp.

Followup to: By author: "Symon" In newsgroup: comp.arch.fpga

Well, having an open implementation would reduce (although probably not eliminate) vendor lock-in.

Some vendors like lock-in; users usually don't. This, of course, can work in reverse: "Well, we'd rather use vendor X right now because we know there is a migration path from X to A if we should need it, and we can use an optimized design for X."

-hpa

Out of curiosity I ran a couple of syntheses+P&R using Quartus II

4.1SP2 Web Edition. This is just synthesizing the mb_cpu as a top level, with all ports going to auto-assigned pins (presumably, internal use could be faster.) Frequency is as reported by Quartus timing analysis. I obviously didn't do anything fancy to try to make it any faster.

None of these inferred any memory or DSP blocks.

Device Optimization LEs used Frequency

EP1C4F324C7 Balanced 2930 60.99 MHz EP1C4F324C7 Speed 3010 76.38 MHz EP1C4F324C6 Speed 3010 84.21 MHz

EP1S10F484C7 Area 2849 70.55 MHz EP1S10F484C7 Balanced 2931 71.89 MHz EP1S10F484C7 Speed 3011 71.60 MHz(!) EP1S10F484C5 Balanced 2931 90.88 MHz

EP2C8F256C8 Balanced 2993 59.27 MHz EP2C8F256C8 Speed 3075 60.72 MHz EP2C8F256C6 Speed 3085(?!) 81.27 MHz

EP2S15F484C5 Balanced 2502 94.79 MHz EP2S15F484C5 Speed 2580 92.83 MHz(!) EP2S15F484C3 Balanced 2504(?!) 126.04 MHz

A few surprises:

- Sometimes "Balanced" gives a faster design than "Speed"

- Sometimes the number of LEs/ALUTs change when the only thing changed is the speed grade of the devices.

-hpa (who wishes Web Edition supported EP2S60 so I could afford to get a devel kit while they're shipping with those :)

That and the fact that it is actually a product they sell.

Cheers, Jon

If Xilinx can establish a case against aeste (the developer of aeMB is working for that company) it will be removed. The question is how much information he had in his possession so that he produced a (reportedly) successful MB implementation.

If he didn't infringe any of Xilinx hardware patents, he should be OK. BTW is the MicroBlaze instruction set patented??? If it is, it is very sad, this can be prohibit you from e.g. implementing a GPL'ed simulator???

Regards

Nikolaos Kavvadias

Actually, I don't see that as such a surprise. I expect that the optimizations are structural and done before timing analysis. So any given structural change (such as duplicating a high fan out driver) may or may not improve the speed after routing even though it increases the amount of logic used.

The fact that the number of LEs change with a change in speed grade would say to me that there is *some* timing analysis being done during synthesis and controls the ultimate result.

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I don't see a big issue with the opcodes, or Xilinx's possible reaction, but such reaction will be proportional to their preceived lost revenue.

# Xilinx benefit if MicroBlaze is in the news

# Such efforts expand usage of, and research in, MicroBlaze

# It can be a usefull second opinion / benchmark

# Xilinx will have trademark rights to MicroBlaze, so they can restrict use of the name. Other examples of this are 6805 uC and i2c instances.

# The open source core is only a tiny portion of system development: you also have compilers/SWdebuggers/HWDebuggers/Libraries, and all of those will have Xilinx license restrictions for Xilinx FPGAs.

Altera would not want to promote this, as they have NIOS.

So, in terms of lost revenues of any signifincance, that leaves the ASIC business, and there it is a trade off of the cost to license the MB from Xilinx, vs do the whole chain 'in house', using the OS as a portion of that.

Q: What does it cost to license MB for an ASIC ?

-jg

Jim,

The license includes rights to use in an ASIC:

Read the licensing agreement terms for details.

You are correct: the more microblazes (microblazing?), the better.

Aust> Uncle Noah wrote:

Thanks for the clarify. Source code is $19,995.

I think ASIC port is covered by this clause ::

"13. Non-Transferable. [] You may provide device programming files ? bit-stream files or PROM files ? and you may provide the data required to implement a silicon mask set to third parties without prior approval solely in order to manufacture the Licensed Product."

and also by this WEB note

"Xilinx also sells Fully Synthesisable Behavioral Source code."

How much for the second pathway ?

-jg

Hi,

Speed vs. Balanced mapping only achieves a small performance advantage on average. I forget exactly how much, but would not be surprised if it were - Sometimes the number of LEs/ALUTs change when the only thing changed

I'll give this one a whirl when I get into work. One possibility is somehow the register packer has chosen not to pack some registers in with luts in the C6 case. The delays the fitter sees are different for a C6 than for a C8, and all optimizations are heuristics so if the inputs change, the outputs usually do too.

And I will take this opportunity to point out that Stratix II was ~39% faster than Stratix I on this particular compile. That's for the naysayers out there who disregard our 50% average performance improvement as marketing b.s. Again, to get a true comparison, we'd have to run multiple seed sweeps on the base Stratix compile and the Stratix II compile.

Paul Leventis Altera Corp.

affect

It has been pointed out to me that we do not recommend that users use synthesis estimates of performance at all, as they do not correlate well to place & route results, even for changes made to the same design. This is not from lack of trying, but due to the disconnect between synthesis (3rd party or integrated) and the downstream place & route tools.

In the upcoming release of Quartus, there will be a new early timing estimator feature that will give quick, accurate estimates of design performance. This is possible since the estimator is part of the fitter (place & route) and thus has access to all the same information and analysers that the optimization tool uses. The estimator uses algorithms and heuristics developed and tuned by the place & route team. It will not give perfect results, but they should correlate quite closely with full-fledged place & route, without the hit in run time.

Regards,

Paul Leventis Altera Corp.