Microblaze data cache question

Hi Marco,

If your matrix is stored in the sdram, you don't need to disable the cache to read/write the contents of the matrix.

The accesses on the xcl bus is only read cachemiss cacheline fills and write through address/data. It's not a general bus for doing a fetch of a whole matrix.

Göran Bilski

I have connected to opb some peripheral which have high throughput. I would use xcl channel to avoid a bottleneck into opb bus.

So, if I have understood, cache is a transparent bus. To read or write into cached sdam I don't need "special" functions, only perform normal operations like a=b, then the system verify if the location of a is into cached sdram. If yes, the system uses xcl chnnel.

Is it correct?

Göran,

I also have the same need: using multiport OPB sdram controller (better yet, the mch-ddr-opb, if it works) to connect OPB and two high bandwidth peripheral (ccd and vga controller).

Can you give some pointer to relevant docs about XCL protocol ? Documentation is _very_ scarce on this subject.

An example with MB for S3/S3E would really jumpstart my design. I would also pay some support fee for that!

There is a small section in MicroBlaze reference guide on the XCL signals.

There is also some timing diagrams on how the MCH based memory controller connects and uses the XCL bus.

Unfortunately there is no document solely about the XCL bus.

To connect the XCL buses is easy in XPS. Just use XPS base system builder for a simple system using MicroBlaze and the mch_opb_sdram controller.

Göran Bilski

Yes, If caches are enabled and the memory access is to a cacheable region it will happen automatically.

Göran Bilski