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Microblaze and software interrupts?

Hi all,

I'm developing a multicore system with up to four Microblaze cores. Now I'm searching for a solution to inform the cores about e.g. messages with a software interrupt. That means, one core writes a message in the shared memory and after that it informs the other cores to read the message. My first idea was to use a GPIO element with interrupts switched on. I tried to write to the element when the message was posted . But there is the problem, that the interrupt is only activated when the data will be changed from outside the microblaze core. So my new idea is to use two GPIO elements and link them together. But it doesn't run and I think, that the problem is the linking of the ports. Has anybody an idea, which ports I have to link (GPIO_d_out or GPIO_IO with GPIO_in or something else) or an idea how to implement software interrupts in such a combination?

I've got a Xilinx ML410 evaluation board.

Thank you for your help.

Reply to
hofmann.juergen
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What abiout using FSLs to communicate between processors? They have a FIFO with somne capacity, they generate interrupts... it is the firmware implem,entation of a queue.

Zara

Reply to
Zara

If you have the ML410 board, then you should already have access to the Xilinx resources for it as well. Take a look at the ML410 Reference Design page and you'll see that Xilinx has provided reference designs for dual-processor configurations. If you dig a little deeper into the projects, you'll see that Xilinx has even gone so far as to provide a core for what you're looking for:

Mutex Mailbox Interface

Here's the ML410 Ref Design page:

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Here's the design w/ the cores that I was mentioning:
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-- Mike

Reply to
morphiend

The problem is, that I have to link every core with each other. A Microblaze core only have eight FSL ports so I could only combine three cores. But I have to check the interrupt idea, perhaps I can use the interrupt signal in my global interrupt controller and all cores react to the interrupt.

Reply to
Hofjue

I solved my Problem with the two GPIOs. You have to design the interrupt GPIO as an input only element an link the GPIO_in port with the GPIO_d_out port of the other GPIO core. If the global interrupt register and the IP-Interrupt register is set correctly, every transition in the second GPIO data register activate an interrupt.

Thanks to Zara and morphiend for their ideas!

Reply to
Hofjue

Hi,

Each FSL port has one input connection (slave) and one output connection (master). So with 8 FSL ports, you can connect from one MicroBlaze to eight other MicroBlazes.

This should be enough for your system.

Göran Bilski

Reply to
Göran Bilski

Yes, that's right. But it doesn't work when MicroBlaze Nr. 3 should communication with MicroBlaze Nr. 2 - or? In my opinion the only solution in this configuration is to use a token ring communication. But then it must be a cyclic communication and not an interrupt driven.

Reply to
Hofjue

Each MicroBlaze has 8 FSL-Ports. So if you have up to 9 MicroBlazes you can connect every MicroBlaze with every other.

Andreas

Reply to
Andreas Hofmann

on

OK - I see. There are eight input AND eight output ports so it's possible to connect 9 MicroBlazes with each other. Thanks for your explanations. The advantage of my solution is, that there is only one interrupt source and all processors can handle it in the same way.

Reply to
Hofjue

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