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Microblaze and custom peripherals

Hi, I am wondering if it is possible to implement adding peripheral(s) to the local memory bus of the Microblaze so as to guarantee that these peripheral(s) have single cycle access to the data and instruction memories of the processor. I am wishing to model very tightly coupled coprocessors, and I have custom peripherals that I have created, but I dont know how to go about connecting them in such a way to guarantee that they have complete single cycle access to the Microblaze's memories, even if it means risking a clock frequency penalty on the processor. Any solutions will be more than appreciated. Thanks!!

Scott

Reply to
ssirowy
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LMB is a single-master bus. You can put peripherals on it, but they cannot bus master - only the microblaze can.

I am wishing to model very tightly coupled

BRAM is dual ported. Connect one port of a BRAM to the microblaze instruction or data LMB, and the other port to your peripheral. Arbitrating simultaneous write accesses to a shared memory is up to you.

The default connectivity with MicroBlaze systems is to tie one port of the BRAM to ILMB, and the other to DLMB. You'll need to watch your bus address mapping scheme, and might need to go for a custom link script to support it.

Regards,

John

Reply to
John Williams

Is there a way to extend the connectivity to allow X amount of peripherals access to the local BRAM's for the processor? Say for simplicity I have 16 custom dividers that I want to instantiate and all require single cycle access to the local processor memory. Is there any way to accomplish this with a Microblaze system? Thanks for your help,

Scott

Reply to
ssirowy

Hi,

On MicroBlaze can be master on the LMB bus. You can have peripherals but no other master. If you want modules to access the BRAM, it can't be done using the LMB.

I would out all these accelerators on the FSL interface.

Göran

Reply to
Göran Bilski

My ultimate goal is to try and investigate how much of an impact adding 1, 2, 4, X amount of peripherals onto the local memory bus has on processor clock impact. I want to be able to allow each coprocessor to have single cycle access, which should in theory impact the clock speed of the Microblaze. Is there a way for me to model and show this impact on the processor clock with the EDK?

Reply to
ssirowy

Is it possible to put a mux in front of the BRAM port for the coprocessor so that I can have X amount of coprocessors, each with single cycle access to that BRAM? If so, is there a simple way to implement that? Im really new to the EDK and Microblaze, and am not really sure how to go about implementing this even if it were possible. Again, thanks for your help!

Scott

Reply to
ssirowy

You have to do a full implementation if you want to see the real impacts. Keep in mind that the data side LMB of MicroBlaze is NOT single cycle but it takes two clock cycles for each load or store. Take a lmb_bram_if_cntrl as the start for your lmb slaves.

One thing, there is no absolute truth on what impact you will see. It will depends on many other different features of your system

- What fpga device

- What speed grade

- What other feature of MicroBlaze is used

- How full is the device

- What LMB slaves that you are using and how they are implemented ...

You should also run Multi-pass PAR (more than 10 passes at least) and take the average.

One question, what is the purpose of this study?

Reply to
Göran Bilski

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