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microblaze and 64 bit memory over PLB bus

Hi

anyone has made it own microblaze soc (eg not using ML401 derivate) where PLB is connected to microblaze OPB over bridge and some peripherals live on the PLB bus? I am struggling with this and can find the problem, for testing I just connected PLB GPIO, it seems to be kind of visible over OPB2PLB bridge, but there is defenetly any writes working :(

This can be done and is used in ML401 ref design, but there seem to be some 'special gotchas' that one has to know to make it work, so if anyone had some problem with similar design and has some hints I would be extremly thankful

antti

Reply to
Antti Lukats
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I'm not quite understanding you here - what "gotchas" are you describing? I was able to easily modify the ML401 reference design for example to make it uClinux-capable, there were no tricks there. The PLB bus had the DDR controller and Xilinx TFT VGA controller. Adding another core on the PLB bus is simple.

One thing to note, that design is very very tight on timing at 100MHz. I did have trouble meeting timing when I started adding and moving cores around in the system. Is that what you are talking about?

Regards,

John

Reply to
John Williams

"John Williams" schrieb im Newsbeitrag news:newscache$0szjgi$c86$ snipped-for-privacy@lbox.itee.uq.edu.au...

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Hi John,

no I had (still have other issues). I did it the hardway - started a fresh new design and added the OPB2PLB bridge, PLB SDRAM etc.. I had some 'thinking' about how to connect the clock's etc.. for testing I added one PLB GPIO, after peeking at ML401 and editing my MHS I got the PLB GPIO to partially working, eg if I write 2 times to the data port then the output is actually updated. So the OPB2PLB bridge and PLB bus are at least partially working. But then I added SDRAM to the PLB and that did not work at all.

I messed up something in the MHS I guess, so probably I need to go the safe route and take the ML401 design and start modifying it.

The bad thing is that when I load ML401 reference design into EDK 7.1 then 'generate address' buttong will cause the XPS to terminate itself :(

I am not yet as far as fighting with the timings yet :)

Antti

Reply to
Antti Lukats

Hi, I am trying to use the plb_tft driver provided in the ML401 reference design with a ML402 board. The reference design "slideshow" doesnot work if I try to download from the EDK enviroinment. Where as, if I use the design stored in the CF card, everything works!! The design stored in the CF card uses system0.bit ot configure the FPGA. I am not sure what it does and the source-code for that design is not known either.

Can someone help me with this. Any suggestion is appreciated.

Thanks, Krishna.

Reply to
krishna1234

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