Hi all, I'm currently working on a FPGA design including a microbalze (as a sub-system). When simulating my design everything seems to be ok but what's bothering me is the following: the time from when I pull down my reset signal until the time the "actual" program start executing is about 100 clk cycles. in thses 100 cycles the PC (program counter) is running almost consecutively.
I would realy appritiete it if any of you can either explain or direct me to an explanation regarding the microblaze program intialization sequence I'm wondering what is it doing "for all this time" ..
p.s. - my design includes an external interrupt handler(maybe it's related).
Thanks in advance, Moti