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Micorblaze post place and route simulation...

Hi guys, I'm trying to do post place and route simulation and generate vcd file to estimate the power with XPower. I tried behavioral simulation and the system was working fine. However as for PPP simulation at the very first in ISE it generated "system_stub_timesim.vhd" and some other files in "netgen" directory in my design. However in the .vhd file the value of all my BRAMs were zero. I added "executable.elf" file to my project in ISE and it seems that there are something in the BRAMs. However I know no better way to populate my BRAMs with data. Anyway the major problem now is that when the modelsim is simulating the design, I'm trying to verify the simulation by monitoring ilmb_lmb_abus and ilmb_lmb_readdbus signals. As for behavioral simulation the flow matched with the assembly file of my software. However in PPP simulation the flow of address generation on ilmb, address bus is insane. It starts fetching from 20000000 instead of 00000000, as well between the rising edge and falling edge of the clock in the same cycle there are so many glitches on address bus which is strange. By the way the ilmb_lmb_abus is 29 bits, so I just assume that it can address the whole memory space needed by 29 bits. Anyone has an idea about the problems that I've faced?

Thanks alot beforehand,

Amir

PS. By the way I'm using ISE 8.1.03i and EDK 8.1.01i

Reply to
amirhossein.gholamipour
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snipped-for-privacy@gmail.com kirjoitti:

By the way, why do you perform post P&R simulation for power analysis? Isn't functional simulation activity output enough? Do you know if post P&R simulation really gives a benefit over functional simulation for power analysis?

Antti

Reply to
antti.tyrvainen

With current FPGAs where routing delay can be more than half of the total delay, p&r results can be quite important in power. How long a route is and how many buffers it goes through certainly impacts the power consumption.

Reply to
mk

mk kirjoitti:

Yes, but does the power tool really need post P&R simulation .vcd for that? Isn't P&R netlist enough?

Can't you use functional .vcd together with post P&R netlist?

Antti

Reply to
antti.tyrvainen

I am not sure what you mean by functional simulation here. If you mean rtl simulation, the answer is no; the nets and the gates (including replicated flops etc) have to match to get an accurate number. If you mean p&r netlist without the associated SDF back-annotation, that would be ok, you don't need timing annotated simulations. VCD gets the changes in the design so you have to simulate what ever is happening in the chip, not necessarily with timing.

Reply to
mk

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Xesium

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