Dear All,
I have an ATM/SDH design that uses the Xilinx MGT with 8b/10b disabled and a 10-bit wide interface.
I drive the Tx side from an external 62.208MHz clock source passed through a DCM: REFCLK => clock_62_208 -- pre DCM TXUSRCLK => clock_31_104 -- post DCM [CLKDV ] TXUSRCLK2 => inverted_clock_62_208 -- post DCM [CLK180]
This gives me a serial line rate of 622.08MHz with my internal logic processing the data at 62.208MHz @ 10-bits wide.
I drive the Rx side from the MGT RXRECCLK. Since the RXRECCLK is 1/20 of the received line rate (1/20th of 622.208MHz = 31.104MHz) I pass it through a DCM to get back to a 62.208MHz source (and inverted): REFCLK => clock_62_208 --pre DCM (external 62.208MHz clock source) RXUSRCLK => recovered_clock_31_104 -- post DCM [CLK0] RXUSRCLK2 => recovered_inverted_clock_62_208 -- post DCM [CLK2X180]
Since processing data that is 10-bits wide is a pain I generate a
20/8ths clock from the RXRECCLK using the DCM to give me (recovered_clock_77_76). I then put the data into a FIFO 10-bits wide @ 62.208MHz and read it out 8-bits wide @ 77.76MHz.This all works and my design operates correctly, the problem that I have is that the recovered clock mechanism I have in place uses a lot of Global Clock Resources (the 3 that are generated by the DCM with RXRECCLK as the source are a real cause for concern).
When duplicating this mechanism for two MGT instantiations. Although the Tx side of the two MGTs share the global clocking resources the Rx sides cannot and as a result my design uses an extra 3 global clocking resources.
Due to other areas of my design with one MGT instantiated I am using
13 Global Clocks. This rises to 16 Global Clocks with 2x MGT instantiation, which is ok as the FPGA I am using XC2VP50 has 16 GCLKs.Now I want to have 4x MGT instantiations and XST is reporting 22 GCLKs and failing to map, which is obvious.
To me the key is to reduce the number of GCLKs used by the DCM that is driven by the RXRECCLK. I assume that it is possible as with a design containing 16x MGT instantiations (as available on the XC2VP50) would clearly not be possible.
I have looked at XAPP763 for inspiration but cannot see how this will help me.
Any ideas?
Regards,
Simon
---- CODE BELOW ----
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
library unisim; use unisim.vcomponents.all; -- used to instantiate the FDC and FDP components
entity channel_rocket_io is port ( cha_bit_stream_out_p : out std_logic; cha_bit_stream_in_p : in std_logic; cha_bit_stream_out_n : out std_logic; cha_bit_stream_in_n : in std_logic; word_stream_out : out std_logic_vector ( 9 downto 0 ); word_stream_in : in std_logic_vector ( 9 downto 0 ); rclk0_62_208mhz_mgt : in std_logic; rclk0_62_208mhz_reset : in std_logic; rclk0_62_208mhz_div2 : in std_logic; rclk0_62_208mhz : in std_logic; rx_buffer_error : out std_logic; tx_buffer_error : out std_logic; rx_reset : in std_logic; tx_reset : in std_logic; nreset_niu : in std_logic; rx_rec_clk_62_208 : out std_logic; rx_rec_reset_62_208 : out std_logic; rx_rec_clk_77_76 : out std_logic; rx_rec_reset_77_76 : out std_logic ); end channel_rocket_io;
architecture RTL of channel_rocket_io is
signal recovered_clock : std_logic; -- used to connect the recovered clock from the MGT to the DCM -- the recovered clock is always a 20th of the data rate (31.104MHz = 1/20th of 622.208MHz)
signal recovered_62_208mhz_div2 : std_logic; -- used to connect the DCM clock (31.104MHz) to the MGT signal recovered_inverted_62_208mhz : std_logic; -- used to connect the DCM clock x2 inverted (62.208MHz) to the MGT
signal inverted_rclk0_62_208mhz : std_logic := '0'; -- used to carry the locally inverted rclk0_62_208mhz signal signal rx_elastic_buffer_full : std_logic_vector( 1 downto 0 ) := B"00"; -- used to connect the rx elastic buffer error signal to the rx_buffer_error signal tx_elastic_buffer_error : std_logic := '0'; -- used to connect the tx elastic buffer error signal to the tx_buffer_error
-- Component definition of MGT - START COMPONENT chanel_rocket_io_mgt PORT( LOOPBACK : IN std_logic_vector(1 downto 0); POWERDOWN : IN std_logic; REFCLK : IN std_logic; RXN : IN std_logic; RXP : IN std_logic; RXPOLARITY : IN std_logic; RXRESET : IN std_logic; RXUSRCLK : IN std_logic; RXUSRCLK2 : IN std_logic; TXDATA : IN std_logic_vector(9 downto 0); TXINHIBIT : IN std_logic; TXPOLARITY : IN std_logic; TXRESET : IN std_logic; TXUSRCLK : IN std_logic; TXUSRCLK2 : IN std_logic; RXBUFSTATUS : OUT std_logic_vector(1 downto 0); RXDATA : OUT std_logic_vector(9 downto 0); RXRECCLK : OUT std_logic; TXBUFERR : OUT std_logic; TXN : OUT std_logic; TXP : OUT std_logic ); END COMPONENT; -- Component definition of MGT - END
-- Component definition of DCM - START COMPONENT rec_clk_dcm PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; CLK2X_OUT : OUT std_logic; CLK2X180_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT; -- Component definition of DCM - END
signal nreset_niu_in : std_logic := '0'; -- used to register the reset the nreset_niu global reset signal signal reset_niu_in : std_logic := '0'; -- used to register the inverted nreset_niu global reset signal
-- the following signal are used to synchronise the global reset to the 77.76MHz recovered clock signal rcclk_77_76_nreset_d : std_logic := '0'; signal rcclk_77_76_reset_d : std_logic := '0'; signal rcclk_77_76_inv_reset : std_logic := '0';
-- the following signal are used to synchronise the global reset to the 62.208MHz recovered clock signal rcclk_62_208_nreset_d : std_logic := '0'; signal rcclk_62_208_reset_d : std_logic := '0'; signal rcclk_62_208_inv_reset : std_logic := '0';
-- the following signals are used to connect the output of the DCM to the global reset synchronisation logic signal local_rx_rec_clk_77_76 : std_logic; signal local_rx_rec_clk_62_208 : std_logic;
signal RCCLK_LOCKED : std_logic; -- used to indicate when the DCM has a lock on the recovered clock from the MGT
begin
rx_buffer_error rclk0_62_208mhz_mgt, -- PRE DCMs 62.208MHz clock source from the external oscillator RXN => cha_bit_stream_in_n, -- negitive pin of the differential receiver pair RXP => cha_bit_stream_in_p, -- positive pin of the differential receiver pair RXPOLARITY => '0', -- no inversion of the rx differential pair, as per the VMETRO instructions RXRESET => rx_reset, -- 1 = RESET MODE, 0 = NORMAL MODE RXUSRCLK => recovered_62_208mhz_div2, -- output of the local DCM RXUSRCLK2 => recovered_inverted_62_208mhz, -- output of the local DCM TXDATA => word_stream_in, -- 10-bit word provided for the paralledl to serial conversion TXINHIBIT => '0', -- always enable the transmitter TXPOLARITY => '1', -- inversion of the tx differential pair, as per the VMETRO instructions TXRESET => tx_reset, -- 1 = RESET MODE, 0 = NORMAL MODE TXUSRCLK => rclk0_62_208mhz_div2, -- output of the DCM inthe pf03_clock entity TXUSRCLK2 => inverted_rclk0_62_208mhz, -- output of the DCM inthe pf03_clock entity RXBUFSTATUS => rx_elastic_buffer_full, -- used to indicate a rx buffer underrun / overrun RXDATA => word_stream_out, -- 10-bit word provided after the serial to parallel conversion RXRECCLK => recovered_clock, -- input to the local DCM TXBUFERR => tx_elastic_buffer_error, -- used to indicate a tx buffer underrun / overrun TXN => cha_bit_stream_out_n, -- negitive pin of the differential transmitter pair TXP => cha_bit_stream_out_p -- positive pin of the differential transmitter pair );
-- Digital Clock Manager Instantiation for the Recovered Clock from the MGT REC_CLK_DCM_INST: rec_clk_dcm PORT MAP( CLKIN_IN => recovered_clock, -- this is the recovered clock from the MGT RST_IN => '0', -- Must be set to '0' to work CLKFX_OUT => local_rx_rec_clk_77_76, CLK0_OUT => recovered_62_208mhz_div2, CLK2X_OUT => local_rx_rec_clk_62_208, CLK2X180_OUT => recovered_inverted_62_208mhz, LOCKED_OUT => RCCLK_LOCKED );
-- OFF CHIP RESET nreset_niu_in nreset_niu_in, C=>local_rx_rec_clk_77_76, CLR=>reset_niu_in); RCCLK_77_76_reset_d RCCLK_77_76_inv_reset, D=>RCCLK_77_76_reset_d, C=>local_rx_rec_clk_77_76, PRE=>reset_niu_in); rx_rec_reset_77_76 nreset_niu_in, C=>local_rx_rec_clk_62_208, CLR=>reset_niu_in); RCCLK_62_208_reset_d RCCLK_62_208_inv_reset, D=>RCCLK_62_208_reset_d, C=>local_rx_rec_clk_62_208, PRE=>reset_niu_in); rx_rec_reset_62_208