I started working with the MGT's recently on a V4 PCI-E development board. I am just using the digital recevier in oversampling mode. Everything is working as expected. I put serial data in and get the bytes out of the backend. The data is asynchronous to the line rate clock and the oversampler works fine.
My question is: how does the oversampler work? What kind of algorithm is used to extract the data? I doubt anyone will answer these questions since the design is proprietary and contains Xilinx IP. But it's worth a shot, right? : )
I simulated the system and found that by closing the data eye down to about 87 percent, the oversampler output the wrong data. I couldn't find any spec for this in Xilinx documentation. And I haven't tried in actual hardware. I am just trying to get a grasp on the boundaries of the oversampling circuit.