Merging the ML403 refence design and the GSRD design

Hello,

As I would like the Ethernet performance from the GSRD design in the ML403 reference design, I would like to merge them into a single system. I tried to use the DCR2OPB to connect the OPB bus with all the slave's, but that will take me some more time to change all lot of address ranges. Therefore I just took a PLB2OPB bridge and attached it to the DPLB bus of the processor, but that gave an error in EDK "more than 1 slave connected to PLB bus .. ". Does someone know what's wrong?

Does someone maybe have a merged version for me ?

Best Regards, Roel

Reply to
electronics_designer
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I believe the PLB in GSRD design is special in a way that it support only 1 master and 1 slave. This is done to save some space

For you purposes you need to use the regular PLB from EDK

Reply to
leevv

Have you contacted Xilinx directly about this? They have a contact email address on the GSRD webpage:

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Paul

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Reply to
Paul Hartke

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