Hello,
I am working on my MS Thesis which involves building a PowerPC based system on the ML410 development board from Xilinx (V4FX60 FPGA). This system will need to do some intense computation (accelerated through hardware) and will need to process a lot of data. I need to squeeze out as much performance out of my memory interfaces as possible, so cache support will be critical. I will be using the APU controller and FCB bus to transfer data to hardware for co-processing, so my CPU speed is limited at 275 MHz.
Right now, I have a design working with the following:
266 MHz CPU (single core for now) 266 MHz FCB (fabric co-processor bus) 200 MHz DDR2 100 MHz PLB 100 MHz OPB PLB BRAMI use the DDR2 primarily as heap space for reading in a large amount of data. The rest of the program sections can go to PLB BRAM or to DDR2. Now, all the cores that I am using are the standard ones that come in EDK
9.1i. As far as the standard memory cores, I am limited to 266 MHz on the DDR2 controller (my DIMM is DDR2-400, so thus I clock it at a lower 200 MHz), and 100 MHz for DDR controller, if I choose to use it (the DDR component on the board can go up to 266 MHz, according to the ML410 manual). So, given these specifications, what is the best I can do for performance? I recently stumbled upon MPMC2 (multiport memory controller - from Xilinx), should I try that? What benefits can it provide (I am not using ethernet controllers). Can that give me any more in terms of performance than what I have setup already? What about OCM - can I leverage that somehow to supplement the caches? Just to recap, these are the memory/controller specifications:DDR2-400 DIMM: memory - up to 200 MHz, controller in EDK - up to 266 MHz (frequency limited by memory) DDR component: memory - up to 266MHz, controller in EDK - 100 MHz (frequency limited by controller)
Any suggestion on this issue would be highly appreciated. I'd like to set-up a base system first before going into the development of the hardware accelerator.
Thanks
- Dmitriy