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maximum life of FPGA based products ????

hi

Manufacturers claim that SRAM based FPGAs can be used in state of the art products and perform well over a long period of time, but my experience negates that.

Two years ago, we developed a "real time face recognition system" using xilinx XC2V6000 on AVNET development kit and delivered the final working product to end user; Who Recently came up with a complaint that the product is not functioning properly. Our technical staff identified that the DCM output (2X clock) is no more in synch with other clocks on the board. same old bitstream was working when we changed the board , and we concluded that the board is faulty.

The faulty board was again working perfectly fine when we used phase shifted DCM output clock. (CLK2X180_OUT)

1-- Maximum working life of FPGA based products is dependant on the device and oscillator characteristics?

2-- What if the same problem arise in commercially manufactured product (whose millions of pieces have been sold) ?

any comments from more experienced users??

regards MH

Reply to
mh
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This may be the result of a silicon mask change that came in. Contact your FAE and they should be able to advise in more detail. I believe that for customers that need this feature there may be a special order code to use.

John Adair Enterpo> hi

Reply to
John Adair

Was this just a problem with the 2v6000? I'm sure there are millions of V-II designs out there that expect their 2x DCM clocks to continue to be phase aligned.

cheers, aar> This may be the result of a silicon mask change that came in. Contact

Reply to
aholtzma

All,

Virtex 2V6000 had a mask change, late in its production life (maybe 18 months after it went to production).

It sped up the global clock resources, which made source synchronous IOs have much more timing amrgin, but it broke CLK2X feedback to the DCM.

This was documented (somewhere, I can't seem to find it on-line now, perhaps it was later fixed...).

And, there was (is?) an order code to purchase the old mask set parts.

This mistake, was in part, my fault. In my haste to get the global clocks performing better (less jitter, less delay), the DCM team failed to re-simulate the CLK2X feedback case (the team I was part of, and the team where it was also my responsibility to simulate changes -- I only verified the CLK0 CLKFB case). Using the CLK0 feedback allowed the DCM to still work (still get a 2X output), but at the expense of using a BUFG from CLK0 to CLKFB (if there was no BUFG on CLK0).

All told, we had three or four customers affected at that time who were unable to find an unused BUFG, and had to fall back to using the old mask set.

Generally, the change was largely a success, as SPI 4.2 cores now worked with plenty of margin.

If this was (is) your issue, I apologize. Since then, even small changes must undergo a complete review, of all blocks, and how they might be affected.

I would contact your Xilinx FAE, who can help you with issue like this quickly and effectively (as we had a solution in place immediately).

Austin

Reply to
Austin Lesea

Austin,

Currently Iam in Pakistan. What is the nearest Xilinx FAE here ??

regards MH

Reply to
mh

List of distributors here

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John Adair Enterpo> Austin,

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John Adair

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Austin

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Austin Lesea

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