The MAX106/104 family is a famous Flash ADC from Maxim, that has PECL outputs based on 3.0 to 5.0V V_CCO. The data sheet for the Xilinx Virtex-II Pro (V2P) claims inputs that are PECL compatible, but only for V_CCO 2.5 V. So on paper, there is a half-volt gap, and one would need some level shifting hardware between them -- maybe just a few resistors?
Speeds are pretty high, 250 to 500 MS/s per digital signal differential pair, which the V2P should handle OK in DDR mode with a 125 to 250 MHz clock.
Has anybody tried this match-up, either directly (by slightly abusing one or both of the parts) or with additional level shifting hardware?
- Larry