Does Xilinx still make a Matlab (not Simulink) -to-gates tool? I don't thi nk so, but I was just wondering. Not that I'm looking for one; I was just wondering. In theory, it would be nice, since I model most things in Matla b before writing Verilog, but such tools usually aren't great at optimizing .
W dniu pi?tek, 6 maja 2016 01:35:04 UTC+2 u?ytkownik Kevin Neilso n napisa?:
hink so, but I was just wondering. Not that I'm looking for one; I was jus t wondering. In theory, it would be nice, since I model most things in Mat lab before writing Verilog, but such tools usually aren't great at optimizi ng.
Do you mean Xilinx System Generator? I think, here you can find more info about its current state.
With best regard, Wojtek
I meant *code* conversion, not Simulink (schematic) conversion.
W dniu poniedzia?ek, 9 maja 2016 19:31:25 UTC+2 u?ytkownik Kevin Neilson napisa?:
So sorry, I'm not aware of availability of such tool now. For C written algorithms you may use their HLS. I've used it a little, and it does its job, however the generated code is o bviously not intended to be human-legible ;-). The generated code is usually better (in terms of logic consumption and max imum clock frequency) than my "quick&dirty" VHDL solutions, but slightly wo rse then "thoroughly handcrafted" VHDL.
Regards, Wojtek
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