Master Xilinx FPGA like Jtag bridge.

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How to make master FPGA to connect to many FPGAs ?

Two FPGAs connected by serial  TDI - TDO, and two fpgas  TMS TCK TDO and TD
I connect to master fpga, master fpga has TMS TDI TDO TCK connected and wor
king to pc normally, it need to make connection JTAG of two fpgas to other  
4 ports or somehow can connect to master's jtag port ?

Re: Master Xilinx FPGA like Jtag bridge.
|---------|-TMS----|------------|-TMS----
| FPGA 0  |-TCK----|            |-TCK----
|         |-TDO----|            |-TDO----
|---------|        |            |-TDI----
    |              |            |
   TDI             |            |
    |              |            |
    |              | MASTER FPGA|
    |              |            |
   TDO             |            |
    |              |            |
|---------|-TMS----|            |
| FGPA 1  |-TCK----|            |
|         |-TDI----|            |
|---------|        |------------|

Re: Master Xilinx FPGA like Jtag bridge.
:
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TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and w
orking to pc normally, it need to make connection JTAG of two fpgas to othe
r 4 ports or somehow can connect to master's jtag port ?

|   |---------|-TMS----|------------|-TMS----
|   | FPGA 0  |-TCK----|            |-TCK----
|   |         |-TDO----|            |-TDO----
|   |---------|        |            |-TDI----
|       |              |            |
|      TDI             |            |
|       |              |            |
|       |              | MASTER FPGA|
|       |              |            |
|      TDO             |            |
|       |              |            |
|   |---------|-TMS----|            |
|   | FGPA 1  |-TCK----|            |
|   |         |-TDI----|            |
|   |---------|        |------------|

Re: Master Xilinx FPGA like Jtag bridge.
On 2/25/2017 12:33 AM, snipped-for-privacy@gmail.com wrote:
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Why do you want the master FPGA to control the others rather than  
loading them all in one chain?  Connect all TMS and TCK lines in  
parallel and connect all TDI and TDO in one big daisy chain.  If the  
slave FPGAs are loaded by the master, where will the data come from?

--  

Rick C

Re: Master Xilinx FPGA like Jtag bridge.
On Saturday, February 25, 2017 at 3:22:21 PM UTC+6, rickman wrote:
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rote:
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nd TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected an
d working to pc normally, it need to make connection JTAG of two fpgas to o
ther 4 ports or somehow can connect to master's jtag port ?
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It is reverse engineering, someone did this but i just want reuse board onl
y

Re: Master Xilinx FPGA like Jtag bridge.
On 2/26/2017 2:27 AM, snipped-for-privacy@gmail.com wrote:
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The JTAG signals to the master chip, do they connect to general I/Os as  
well as to the FPGA JTAG signals?  Or just JTAG or just I/Os?

You didn't say where you expect the data to come from to program the  
chained slave FPGAs.  Is it supposed to come from the main JTAG port as  
if it was talking to the slave chain?  Or will the master FPGA have a  
separate interface from an MCU or a Flash chip?

What is your overall plan?

--  

Rick C

Re: Master Xilinx FPGA like Jtag bridge.
On Sunday, February 26, 2017 at 4:21:49 PM UTC+6, rickman wrote:
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 wrote:
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 and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected  
and working to pc normally, it need to make connection JTAG of two fpgas to
 other 4 ports or somehow can connect to master's jtag port ?
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 only
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Hi, i am also doing same thing and also have same question )))). I think fi
rst need program master FPGA and then normal masters JTAG can be used as JT
AG for other tributary fpgas . may be/

Re: Master Xilinx FPGA like Jtag bridge.
On Sunday, February 26, 2017 at 4:21:49 PM UTC+6, rickman wrote:
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 wrote:
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 and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected  
and working to pc normally, it need to make connection JTAG of two fpgas to
 other 4 ports or somehow can connect to master's jtag port ?
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 only
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Slave FPGAs connects to USER I/O ports. for example:
TMS of salve FPGA chip connects to user i/o pin  CC
TDI of slave FPGA chip connects to user i/0 pin  VRP
TCK of slave FPGA ship connects to user i/o pin  CC

Re: Master Xilinx FPGA like Jtag bridge.
On 3/24/2017 7:30 AM, snipped-for-privacy@gmail.com wrote:
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What do you connect the user I/O of the master to internally?  If you  
try using the JTAG on the master it will control the master, no?

--  

Rick C

Re: Master Xilinx FPGA like Jtag bridge.

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Perhaps you are looking  for something similar like Altera JAM Player  
for embedded.

Take a look here  
https://www.altera.com/support/support-resources/support-centers/devices/programming-tools/jam-stapl/tls-jam-embedded.html

There is pice of C code able to send chip image from embedded system to  
another fpga.

Unfortunatell I don't know X as good as I would like to.

BR

Adam

Re: Master Xilinx FPGA like Jtag bridge.

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programming-tools/jam-stapl/tls-jam-embedded.html
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I dont know C

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