Master Serial Programming

Hi ,

I have general question regarding the Master Serial Programming mode . In the Master Serial Programming mode , FPGA drives the clock . But ,how will the FPGA know that there is relevant and complete data present on the PROM . Is there any mechanism to tell the FPGA that the configurable data is present on the PROM and FPGA to initiate the clock.

Thanks in Advance , Sowjanya

Hi,

There is a hand-shaking protocol, between PROM and FPGA, which varies for different FPGA vendors. Specific to Xilinx FPGAs, the steps involved in configuration of FPGA are

1.Once the power supply voltage to PROM reaches above a pre-definced threshold, it asserts a signal, to reset all config. memory on FPGA.

2.Once all config. memory is reset, FPGA acknowldges PROM, and starts giving out clock to PROM.

3.When PROM receives clock and ack, it starts sending out the config,bits serially or parrallely( as per config. mode selected) through the data bits.

4.When final config. byte is received by FPGA and doing config, FPGA asserts DONE signal, which drives PROM to power save mode. FPGA stops sending clock also.

I h> Hi ,

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In just a few words, the FPGA doesn't know at the begining if the prom has "relevant" (and it doesn't have to know) data it just run the clock enable the prom (INIT->\CE) which resets the internal counter inside the prom and the prom will start to shift out the bitstream. The FPGA will parse the incoming bitstream to detect a valid header (0xFFAA55 not sure if this is correct - just check the docs) and everything following this sequence is considered bitstream for the configuration mechanism (and will count for the CRC check)

Short: in master serial mode the fpga is assuming that the prom has the bitstream already.

Aurash

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/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
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