Marking Flase paths for Timing Ignore + Virtex 2 Pro support

Hi, I have two questions. ============================================== Marking False paths for timing ignore in a multiple clock design: =============================================== I have a design with three clocks. All clocks are indpendant and are not derived. The data originating in these clock domains cross other clock domains. I have used synchronizers (fast to slow and slow to fast) wherever applicable. However for correct timing analysis and timing closure, I need to identify signals which cross multi clock domain. The design is synthesized for Spartan3 xc3s1000. I am using timing constraints editor to identify such paths and put them in the ucf file with the 'TIG' against them. The way I am doing it is a bit cumbersome. First, I identify all signals(FFs) which are clocked on one clock, make a domain of them. Similarly, I identify all other signals(FFs) which are clocked on other two clocks and make two seperate domains. Identifying the signals is a very tiring process as one has to go through all the RTL files to look for 'always' blocks and the signals in those blocks. Once the domains have been created, the domains are 'Tiged' against each other using the following syntax(an example).

TIMESPEC "TS_uC_to_66" = FROM "domain_clk_uC" TO "domain_clk_66" TIG; TIMESPEC "TS_66_to_uC" = FROM "domain_clk_66" TO "domain_clk_uC" TIG;

The problem is, this whole process takes allllllooooot of time and prone to errors. Is there a better and fast way to accomplish the same. Do I really need to add all clocked signals? The ucf file generated in this manner takes 7-8 thousand of lines (at least for my design).

============================================== Virtex 2 Pro support in higher versions of ISE: =============================================== I have ML310 board with Virtex 2Pro xc2vp30 on it. ISE 7.1 has the support for the particular family and deivce however, I dont see the same part appearing in ISE 8.1 or ISE 9.2. Has the part been discontinued? If not, how can I add the library for the particular device in ISE 8.1 or ISE 9.2.

Thanks in advance

Farhan

Reply to
maverick
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NET "clk_uC" TNM=FFS "domain_clk_uC"; NET "clk_66" TNM=FFS "domain_clk_66";

I guess you didn't read the constraints guide.

What's more worring is that you have so many signals crossing clock domains. You could be headed for a world of hurt.

Happy days, Syms.

Reply to
Symon

NET "clk100MHz" TNM = tnm_100domain; NET "clk200MHz" TNM = tnm_200domain;

# cross-clock exceptions - all cross-clock signals are treated as asynchronous. TIMESPEC "TS_crossclk1" = FROM "tnm_100domain" TO "tnm_200domain" TIG; TIMESPEC "TS_crossclk2" = FROM "tnm_200domain" TO "tnm_100domain" TIG;

Reply to
JuanC

You should still have XC2VP30 support in ISE 9.2. (I think it is even included in the webpack version of ISE 9.2 now.)

However, I have heard rumors that EDK 9.2 doesn't support XC2VP* devices but I haven't verified it myself since I'm not a big user of EDK.

/Andreas

Reply to
Andreas Ehliar

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