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Mapping problem due to invalid pins in UCF file

Hi.. I am currently working with Xilinx ISE 6.3i ..The design is in VHDL..I tried adding some extra inputs and outputs to the top level entity and hence made the corresponding changes to the UCF file. But when I try implementing the design, it shows errors in the Map process as follows:

1) The extra inputs I added in the UCF file are shown as invalid

I have just used the format

for example:

NET "my_input_name" LOC = "P34" ;

2)Should I also add INST?

If so how should I do that and is it for all the component instantiations?

3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?

I then removed the unused inputs and outputs but it still shows the same error...

Any suggestions are welcome..

Thanks in advance,

Methi

Reply to
methi
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--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply to
Aurelian Lazarut

Hi Aurash,

These are the error messages:

ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such site on ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such site on ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data is invalid: No such site ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data is invalid: No such site ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data is invalid: No such site ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data is invalid: No such site ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data is invalid: No such site ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data is invalid: No such site ERROR:MapLib:681 - LOC constraint P119 on dig_video_out is invalid: No such ERROR:MapLib:681 - LOC constraint P118 on dig_video_out is invalid: No such ERROR:MapLib:681 - LOC constraint P130 on dig_video_out is invalid: No such ERROR:MapLib:681 - LOC constraint P26 on dqm is invalid: No such site on the ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address is invalid: No such ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address is invalid: No such ERROR:MapLib:681 - LOC constraint P131 on dig_video_out is invalid: No such ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No such site on ERROR:MapLib:681 - LOC constraint P103 on dig_video_in is invalid: No such ERROR:MapLib:681 - LOC constraint P104 on dig_video_in is invalid: No such ERROR:MapLib:681 - LOC constraint P105 on dig_video_in is invalid: No such ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such site on ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site on the ERROR: MAP failed

Thankyou, Methi

Aurelian Lazarut wrote:

VHDL..I

and

Reply to
methi

This basically tells you that there is no pin "P130" on your FPGA, which is understandable... Haven't seen any FPGAs with 130 rows/columns around lately :) You're trying to route the signal dig_video_out to a pin that does not exist. Same with most of the other signals, your FPGA can't possibly have pins like that. Check your pin assigments again.

cu, Sean

Reply to
Sean Durkin 

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply to
Aurelian Lazarut

Hi Aurash and Sean..

Thanks for helping me out..

I am using XC3S400_4TQ144....

There are totally 144 pins...

And the connections have been made on the board..but the FPGA isnt programmed as yet...

Thats what I was try> what part/package are you targeting?

such

such

No

No

No

No

No

No

invalid:

invalid:

invalid:

invalid:

invalid:

invalid:

such

invalid:

invalid:

invalid:

such

site

the

Reply to
methi 

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply to
Aurelian Lazarut

Hi Aurash,

My Map report is as follows:

It doesnt show any removed signals..

How do I insert IO's when I synthesize the design?...Do u mean include them in the code?...If so , yes I have included them in the code(top level entity)...

------------------ Release 6.3.02i Map G.37 Xilinx Mapping Report File for Design 'top_1190_mem'

Design Information

------------------ Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o top_1190_mem_map.ncd top_1190_mem.ngd top_1190_mem.pcf Target Device : x2s200e Target Package : pq208 Target Speed : -6 Mapper Version : spartan2e -- $Revision: 1.16.8.2 $ Mapped Date : Mon May 23 17:19:17 2005

Design Summary

-------------- Number of errors : 21 Number of warnings : 0

Section 1 - Errors

------------------ ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P1 on sd_ram_data is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P2 on sd_ram_data is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P25 on sd_ram_data is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P14 on sd_ram_data is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P13 on sd_ram_data is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P12 on sd_ram_data is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P119 on dig_video_out is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P118 on dig_video_out is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P130 on dig_video_out is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P26 on dqm is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P50 on sd_ram_address is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P51 on sd_ram_address is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P131 on dig_video_out is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P128 on reset_bar is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P103 on dig_video_in is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P104 on dig_video_in is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P105 on dig_video_in is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'. ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

Section 2 - Warnings

--------------------

Section 3 - Informational

------------------------- INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary

---------------------------------

Section 5 - Removed Logic

-------------------------

This is wat the Map report shows.....

Thanks, Methi

Aurelian Lazarut wrote:

case

the

invalid:

invalid:

invalid:

invalid:

invalid:

invalid:

such

entity

Map

Reply to
methi

are the pin names correct? because i thought in S3 they use a letter/number assignment and not p/nimber?

Reply to
Yttrium

Hi..

This is the way I have written the assignment in the UCF file..not sure if this is correct:

for example:

NET "dig_video_out" LOC = "P113" | IOSTANDARD = LVTTL ; NET "dig_video_out" LOC = "P112" | IOSTANDARD = LVTTL ; NET "dqm" LOC = "P26" | IOSTANDARD = LVTTL | SLEW = FAST ; NET "dqm" LOC = "P27" | IOSTANDARD = LVTTL | SLEW = FAST ; NET "pal_ntsc" LOC = "P77" | IOSTANDARD = LVTTL ; NET "probe" LOC = "p78" ; NET "ref_27mhz" LOC = "P53" | IOSTANDARD = LVTTL ; NET "sd_clk" LOC = "P30" | IOSTANDARD = LVTTL | SLEW = FAST ; NET "sd_clk_en" LOC = "P32" ; NET "sd_cs" LOC = "P35" ; NET "sd_ram_address" LOC = "P60" | IOSTANDARD = LVTTL | SLEW = FAST | PULLUP ;

I havent written anyth> are the pin names correct? because i thought in S3 they use a

letter/number

include

code(top

top_1190_mem.ngd

such

such

No

No

No

No

No

No

invalid:

invalid:

invalid:

invalid:

invalid:

invalid:

such

invalid:

invalid:

invalid:

such

site

the

signal

clock

the

isnt

to

No

No

invalid: No

No

such

in

the

invalid

shows

Reply to
methi

After some investigation with the design files provided by the OP, it seems that the design files were created for a different part, that will explain why MAP errors out. It's a good practice, if the user change the targeted part, to clean the project files (form menu Project -> Cleanup Project Files) and of course take care of the UCF file which will not match the new target part.

Aurash

methi wrote:

--
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
Reply to
Aurelian Lazarut

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