Mapping port for simulation only in VHDL

Hi all,

I would like to use a signal in the a testbench that is declared in one of the subblocks of the top.

This question might obvious, but I cannot find any other way to use subblock signals from a top of a design ONLY for simulation purposses.

What I usually do is to add those signals as ports in each entity beginning from the bottom of the design and continuing the hierarchy until I arrive to the top. In order not to consider them in the synthesis I add "synthesis translate off/on" comments.

Here you are an example:

Imagine that I want to instantiate the internal signal of the subblock1 from the top

entity top is port( -- synthesis translate_off tb_out : out std_logic; -- synthesis translate_on ... ); end top;

architecture arch of top is begin

uut: subblock1 port map( -- synthesis translate_off internal => tb_out, -- synthesis translate_on ... ); end;

Then I instantiate the top in the same way from the testbench.

I know that in verilog there is another way to refer to a signal that is declared in subblock, just with something like this:

"top.subblock1.internal"

Any suggestion?

Thanks in advance,

Arkaitz.