mapping error

Hi all;

i am trying to use lock_pins to lock theinstantiated LUTs pins , iam using ISE 9.1 and my family is virtex 2 pro, first i tried to do this using ucf file and it works, but i want to do this by adding this attribute in the vhdl file , i got an error during the mapping phase , i don't know what is it

what i wrote in the vhdl

attribute INIT : string; attribute INIT of LUT1_o0_s: label is "2"; attribute lock_pins: string; attribute lock_pins of LUT1_o0_s: label is "true"; begin

LUT1_o0_s : LUT1 generic map ( INIT =>"01") port map (O => o0_s, I0 => aleft0right);

and the error

Using target part "2vp30ff896-7". Mapping design into LUTs... ERROR:MapLib:688 - Pin true in LOCK_PINS constraint does not exist.

Error found in mapping process, exiting... Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.

thanks fatma