Manually creating a LUT in VHDL

Yes it is possible. The following URL will give some information for example:

(Answer record 10068)

/Andreas

I'm not sure which you are asking for: A generic look-up containing your data coded as RTL, or instantiating a LUT-4 primitive with your init data.

For the former:

type int_array is array(natural range ) of integer; constant lut_data: int_array(0 to 15):= (0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0); signal lut_addr: unsigned(3 downto 0); signal lut_out: unsigned(7 downto 0); attribute syn_keep of lut_out: signal is true; begin

LUT_out

Thanks, all of your posts were very helpful.

David