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Malfunctioning dual port block ram.

Hi,

I have instantiated a dual port block ram through coregen with a 128 bit write only port and a 32 bit read only port.

I am using chipscope to debug the FPGA and when I view all signals connected to ram, all write port signals are correct, but the data read out from read port is sometimes correct, and other times it is garbage data.

Could somebody suggest a solution to this problem. Is it a timing problem? (the frequency of operation is low around 10 Mhz) -- Aniket Naik Computational Mathematics Laboratory, Tata Institute of Fundamental Research, India.

Reply to
Aniket Naik
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Possibly not the same problem, but I've seen issues recently with a Core Gen RAM not being synthed properly by XST. I switched over to Synplify and the problem disappeared.. My faith in XST is limited!

Cheers, Jon

Reply to
Jon Beniston

I didn't think that Coregen'ed stuff *was* synthesised - does the synth not see it as a black box? Then the downstream tools find the EDIF netlist to fill in the gap..

Cheers, Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Reply to
Martin Thompson

Could it wire up the black box wrong? Functional sim worked okay and post-translate sim didn't (neither did h/w). It could have been the translate prog that screwed up I guess, but I didn't have the time or will to find out. Whenever things like that have happened before, switching to Synplify always fixed it. Cheers, JonB

Reply to
Jon Beniston

That sounds more likely - or the synthesis of something else related to the RAM (like a WE or address counter for example)

It's not bug-free either....

Cheers, Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
Reply to
Martin Thompson

Which FPGA are you using? Some Spartan2 parts had some problems with simultaneous read/writes. I think the 2Es are OK as are the Spartan3s and Virtex2s.

Are the read and write ports using the same clock?

Are you attempting to simultaneously read and write from the same address?, if so don't do that.

Reply to
General Schvantzkoph

I had this problem with leonardo version 2001. I've just changed to leonardo

2002 and it was working well.
Reply to
spr

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