I'm using EDK 9.1i. I have created custom IP using "Create or Import Peripheral", modified the VHDL files, and then imported it into my project using "Create or Import Peripheral" once more.
If I make changes to the VHDL files associated with my peripheral, what must I do to get these changes into my project?
Do I need to delete the instance of my peripheral and import it again from the CIP wizard, or is there another way?
Thanks.
I have found under 9.1 that editing the VHDL files down in pcores is not always enough to get the changes in. To be sure to get the changes compiled, I go to project -> clean all generated files, and then quit the project and delete the "__xps" directory.
-Jeff
No, you do not need to delete the instance of your peripheral. Just delete the generated netlists using hardware/clean netlist or hardware/ clean hardware, and re-build the project using generate netlist/ hardware. Hope this helps, Guy.
These approaches seem to work. Thanks.
Yes, it works but the whole project will be re synthesized which is time consuming. Instead, you can change a parameter of your IP in mhs - and that IP only will be re synthesized and merged with the rest of the project. Another option is to use OPTION CORE_STATE =3D DEVELOPMENT in the IP's mpd and the core will be synthesized every time you run platgen. More detail in C:\EDK\doc\usenglish\psf_rm.pdf page 38
Yes, these methods are very slow. I'm trying your method, but I'm not sure how to get it working from within EDK. I set OPTION CORE_STATE =3D DEVELOPMENT in the mpd and when I rerun "Generate Netlist" I get the output "make: Nothing to be done for `netlist'." platgen is not being run. Is there a way to get it working from within EDK?
Thanks
Try using Project> Rescan user repositories.
and while we are on this subject, why doesn't edk create a real makefile with all the necessary dependencies. then, when you change anything, all the necessary files would be rebuilt.
this would also get rid of the cache, because automatically, only dependent files would be rebuilt.
it seems like xilinx got 90% of the way there with make and then fumbled the last 10%.
software people build gargantuan projects entirely with make. why can't edk?
alan nishioka
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