Make program stop

Verilog describes logic, and it is possible to make logic to do that. You can use a counter, for example.

AL also wrote:

This is the property of RAM, which is easy to write in verilog, it looks pretty much like a C array. Don't forget to clear it before writing to it. To increase the count you will need to read it, increment it, and write it, most likely in separate clock cycles (clock edges if you are really lucky).

Good luck!

-- glen

Thanks glen for the response, but what about making the program stop completely and pop up a message that says something like "ERROR", is there a way to implement that? I have tried using "disable" but that won't compile, I think it was unsupported or something. Thanks, Ann

completely and pop up a message that says something like "ERROR", is there a way to implement that? I have tried using "disable" but that won't compile, I think it was unsupported or something. Thanks, Ann

What program? Verilog describes the layout of hardware. I suppose you could connect all of your I/O pins to ground (or use tri-state and disconnect them), but you can't stop electrons moving in the wires!

Alun Harford

Hi, I didn't mean stop completely but just stop what it's doing, but now that I think about it, I guess I can just make it output some kind of default value or something. But what about get it to pop up a message "DONE" or "ERROR" or something so that the user can see? Thanks, Ann

that I think about it, I guess I can just make it output some kind of default value or something. But what about get it to pop up a message "DONE" or "ERROR" or something so that the user can see? Thanks, Ann

On what? It's an FPGA - it has wires going in and wires coming out. If you've turned it into something fancy that can output to a screen (or printer, serial port or whatever) then the answer depends on how you did that. If you're running a verilog simulator, there will probably be calls you can make - but I don't think I've ever used them so I can't remember what they are (I'm sure I'll regret that when it gets asked in my exams, but there we go)

Alun Harford

I googled "verilog stop" and quickly came back with $stop. (Note: I haven't used verilog [much] in about 8 years. Been using the other major HDL.) E.g.,

I don't know if verilog has a direct equivalent to VHDL's "report" and "assert" commands, but I'm sure you could work something out with one of the following (from that link):

$display("text_with_format_specifiers", signal, signal, ... );

Prints the formatted message once when the statement is executed during simulation. A newline is automatically added to the text printed.

$write("text_with_format_specifiers", signal, signal, ... );

Like $display statement, except that no newline is added.

$strobe("text_with_format_specifiers", signal, signal, ... );

Like the $display statement, except that the printing of the text is delayed until all simulation events in the current time step have executed.

Jason

Hi Jason, But isn't that for simulation only? I want something to display after I download the program to the FPGA and ran it. Thanks, Ann

I think you're confused about the capabilities of FPGAs. You can think of an FPGA as a bunch of logic with input wires and output wires. To display any kind of output message you will need some kind of output peripheral, such as an LCD. Or you can go even simpler than that and use a few 7-segment displays. You can then interface your display device with the FPGA and then write HDL code to drive the display and make it display what you want.

Ask> Hi Jason, But isn't that for simulation only? I want something to

display after I download the program to the FPGA and ran it. Thanks, Ann

Hi, Thanks for all the helpful responses. But I still have another question. Has anyone ever used JTAG to read back a register content??? I ran into some problem doing this, and need some help. When I put a constant number into the register and read it back, it works, but when I have that number changed depending on an if else statement, it doesn't work anymore. For example, in the following code: always @(posedge CLK_IN) begin if(RESET) begin num = 20+1; end else begin num =

1+1; end It would give me 00010011 or 21 even though the RESET signal has changed. I tried using the CASE statement instead: always @(posedge CLK_IN) begin case(RESET) 2'd0: num = 20+1; 2'd1: num = 2+2; default: num = 3+4; endcase end Now it always gives me 00000000 when I tried to read it back. Do you have any idea why? Thanks, Ann

This is a synchronous reset, which says to set num to 21 if RESET is high on a rising edge of CLK_IN. If RESET is low on a rising edge it sets num to 2.

In logic terms, RESET is the enable for a FF, and CLK_IN is the clock.

(Also, RESET is usually used to describe setting to zero.)

-- glen

Hi Glen, I still don't understand what the problem is though :-( So when I changed RESET, shouldn't the register be changing as well???? Thanks, Ann

Hi Glen, I still don't understand what the problem is though. So when I changed RESET, shouldn't the register be changing as well???? Right now it's not doing that, I kept getting 21 out for some reason. Thanks, Ann

Hi Glen, I still don't understand what the problem is though. So when I changed RESET, shouldn't the register be changing as well???? Right now it's not doing that, I kept getting 21 out for some reason. If I change always @(posedge CLK_IN) to always @(CLK_IN), then it works, do you know why???? Thanks, Ann

always @(CLK_IN) begin

means to do those operations on either edge of the clock. As far as I know, real flip-flops don't do that, and the synthesis programs won't compile it, but it will simulate.

No, it does not sense change in RESET. An asynchronous reset should be

always @(posedge CLK_IN or posedge RESET) begin if(RESET) cnt

But the FPGA communicates with JTAG somehow, and JTAG is connected to the parallel port of the PC, so can't we use that connection to write code to get the PC to display something after some kind of event? Thanks, AL

Hi Zerang Shah, But the FPGA communicates with JTAG somehow, and JTAG is connected to the parallel port of the PC, so can't we use that connection to write code to get the PC to display something after some kind of event? Thanks, AL

Hi, I take that back, it works for always @(posedge CLK_IN) as well as always @(CLK_IN), but only for very simple logic, if else and case statement, etc. For harder logic such as a counter, it read back 00000000. Does anyone know why?

Hi, I take that back, it works for always @(posedge CLK_IN) as well as always @(CLK_IN), but only for very simple logic, if else and case statement, etc. For harder logic, it doesn't work, only read back 00000000 . Does anyone know why?

always @(posedge CLK_IN)

says that the statements within the block are executed on the rising edge of CLK_IN. If they are not doing that, or if the are getting executed at other times then you have found a bug.

reg q; always @(posedge clk) q=d;

implements the usual edge triggered flip-flop like the 74LS74. If you put more in the always block you will get extra logic before your flip-flop;

always @(posedge clk) q=d1 & d2;

is an AND gate and a FF.

reg [3:0] q; always @(posedge clk) q=q+1;

is a four bit adder followed by four FFs, otherwise known as a synchronous counter. (If you add up/down it could be a 74LS193)

-- glen