Make a signal free for glitches?

I have a CPU register block where I use the outputs (wich are supposed to be static) to control other clock domains.

The question rises; will these signals coming out of a flip-flop be guaranteed free for glitches?

For a synchronous design, there is a setup&hold condition in the cpu clock domain where this signal will be stable, but how about the rest of the time window? Is there any tricks to make this guaranteed glitch free?

The reason I ask is that I want to use this signal to mux (using 2 input muxcy to avoid lookup table glitches) a clock signal and I want the outgoing clk to be glitch-free. Maybe I have to route the switching signal thru a bidir pin and put a capacitor on it.

Note:I WILL treat this new clk as a new clock domain, and the domain WILL be reset properly after switching clock.

Reply to
Morten Leikvoll
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Morten Leikvoll schrieb:

The output of a flipflop is always glitch free (when setup and hold times are met)

This is another problem. In a tecXcluse a long time ago there was a glitch free clock MUX. They are also as hard macros in Virtex-II / Spartan 3 etc.

Autsch. Dont do this! This is just a crude work around for, hmmmm,. Dont do it!

Regards Falk

Reply to
Falk Brunner

There is a guaranteed glitch-free clock multiplexer design in "six easy pieces", #6 Find it under TechXclusives on the Xilinx website, or click on:

http://www.xil> I have a CPU register block where I use the outputs (wich are supposed to be

Reply to
Peter Alfke

Thanks for this solution! :) I still miss an explanation why the muxcy solution may fail, counting out the possible glitches at the point of switching, wich I intend to take care of using synchronous resets.

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Reply to
Morten Leikvoll

On second thought.... Are you sure this is safe? What if the three right gates are implemented in a lookup table (they probably will, won't they)? Having 2 different clocks into a lookuptable sounds very risky for the output.

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Reply to
Morten Leikvoll

I am sure it is safe. This circuit has proven to be glitchfree, as described in the words around it (metastability lass than half a clock period) In general: Whenever you change one input of a LUT, there is no glitch at the output if the two input addresses generate the same output level. I documented this 15 years ago... Peter Alfke, Xilinx

Reply to
Peter Alfke

This information doesn't seem to have made it into the datasheets, which is why I asked that question a few months ago.

Eric

Reply to
Eric Smith

This is what I wrote 15 yars ago, and it still applies: "..Note that there can never be a decoding glitch when only one select (address) input changes. (Even a non-overlapping decoder cannot generate a glitch problem, since the node capacitance will retain the previous logic level until the new pass gate is activated a fraction of a nanosecond later) When more than one input changes "simultaneously", the user must analyze the logic output for any possible intermediate address code permutation. If any of them would produce a different output, the user must assume that a glitch might occur. If all of the possible address variations produce the identical output, then the user can be sure that there will be no glich at the output.

The designers of synchronous systems generally do not worry about such glitches, since synchronous designs are inherently immune to data glitches, except on clocks and asynchronous Set or reset inputs."

I hope this helps Peter Alfke, 15 years later still at Xilinx...

Reply to
Peter Alfke

It's not a very useful UR - generates following from Mozilla:

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Sorry... Technical difficulties with the Xilinx.com web site have been solved. If you are continuing to have difficulty accessing Xilinx.com, you may need to exit your browser software and restart it. Please accept our apologies for any difficulties you have experienced.

obviously not solved :(

Reply to
fpga_toys

Seems to have moved to here ?

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-jg

Reply to
Jim Granville

Thanks a lot Peter. It DID help sort out this protential problem :)

Btw.. I compressed the URL at

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Reply to
Morten Leikvoll

their webmaster is on hawai vaccation as usual !

antti

Reply to
Antti

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