I have a CPU register block where I use the outputs (wich are supposed to be static) to control other clock domains.
The question rises; will these signals coming out of a flip-flop be guaranteed free for glitches?
For a synchronous design, there is a setup&hold condition in the cpu clock domain where this signal will be stable, but how about the rest of the time window? Is there any tricks to make this guaranteed glitch free?
The reason I ask is that I want to use this signal to mux (using 2 input muxcy to avoid lookup table glitches) a clock signal and I want the outgoing clk to be glitch-free. Maybe I have to route the switching signal thru a bidir pin and put a capacitor on it.
Note:I WILL treat this new clk as a new clock domain, and the domain WILL be reset properly after switching clock.