For those interested in FPGA CAD and architecture research, we are pleased to announce the full release of the Verilog-to-Routing (VTR) project version 1.0. VTR consists of a suite of CAD tools, circuit benchmarks, FPGA architectures, and experiment scripts to aid those in the community to explore new FPGAs as well as algorithms to map to future FPGAs. This effort is an international collaboration of researchers, and consists of three software tools: ODIN II for Verilog Elaboration, ABC (from Berkeley) for Logic Synthesis, and VPR for packing, placement, routing and timing analysis.
You can find detailed information on the new release here:
This new full release has many new features and has been extensively tested. It is also worth noting that all three tools are Open Source. In particular, that is now true of VPR, which is new.
This new version of VTR is now fully timing driven in the packing, place and routing phase of VPR. The previous, alpha release (which was not timing-driven), enabled the description of far more complex logic blocks, including the popular Fracturable blocks (such as LUTs than can operate as one big LUT or two smaller LUTs) in modern commercial FPGAs. There is also explicit support for hard memories and multipliers from the Verilog level on down.
This release contains architecture files and benchmark circuits that make use of Fracturable LUTs, memories and multipliers. The set of benchmark circuits in this release are from real applications many of which contain multipliers and memories. The largest of these circuits is almost 100,000 6-LUTs. In additional to these benchmarks, we also included the old MCNC circuits as well as a set of circuits that use embedded floating-point cores.
We provide CAD/Architecture scripts that show how to run various experiments. As good science needs to be repeatable, we have included our results so that users of VTR can easily replicate the same results that we obtained.
We made a strong effort to make a more user friendly build experience. Building VTR should be as simple as entering make in the main directory. Testing the flow should be as easy as running a script that reports what successfully built and what did not.
If you are interested in downloading VTR or getting more information about it, please visit our website here:
The VTR development team:
University of Toronto: Jason Luu, Jason Anderson, Vaughn Betz, Opal Densmore, Cong Wang, Peter Milankov, Jonathan Rose University of New Brunswick: Kenneth B. Kent, Ash Furrow, Paddy O'Brien, Joey Libby, Shubham Jain, Konstantin Nasartschuk, Andrew Somerville
University of British Columbia: Jeff Goeders, Eddie Hung
U. Penn: Rafi Rubin
U Miami, Ohio: Peter Jamieson
City University of Hong Kong: Chi Wai Yu
(Many thanks to Robert Brayton and Alan Mischenko at U.C. Berkeley for the use of the ABC Logic Synthesis tool).